/*
* board/renesas/alt/alt.c
*
- * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014, 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#define ETHER_MSTP813 (1 << 13)
#define IIC1_MSTP323 (1 << 23)
#define MMC0_MSTP315 (1 << 15)
+#define SDHI0_MSTP314 (1 << 14)
+#define SDHI1_MSTP312 (1 << 12)
+
+#define SD1CKCR 0xE6150078
+#define SD1_97500KHZ 0x7
int board_early_init_f(void)
{
/* MMC */
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
#endif
+
+#ifdef CONFIG_SH_SDHI
+ /* SDHI0, 1 */
+ mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312);
+
+ /*
+ * SD0 clock is set to 97.5MHz by default.
+ * Set SD1 to the 97.5MHz as well.
+ */
+ writel(SD1_97500KHZ, SD1CKCR);
+#endif
return 0;
}
r8a7794_pinmux_init();
/* Ether Enable */
+#if defined(CONFIG_R8A7794_ETHERNET_B)
+ gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
+ gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
+ gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
+ gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
+ gpio_request(GPIO_FN_ETH_LINK_B, NULL);
+ gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
+ gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
+ gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
+ gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
+ gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
+ gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
+ gpio_request(GPIO_FN_ETH_MDC_B, NULL);
+#else
gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
gpio_request(GPIO_FN_ETH_RX_ER, NULL);
gpio_request(GPIO_FN_ETH_RXD0, NULL);
gpio_request(GPIO_FN_ETH_MAGIC, NULL);
gpio_request(GPIO_FN_ETH_TXD0, NULL);
gpio_request(GPIO_FN_ETH_MDC, NULL);
+#endif
gpio_request(GPIO_FN_IRQ8, NULL);
/* PHY reset */
unsigned char enetaddr[6];
ret = sh_eth_initialize(bis);
- if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+ if (!eth_env_get_enetaddr("ethaddr", enetaddr))
return ret;
/* Set Mac address */
int board_mmc_init(bd_t *bis)
{
- int ret = 0;
+ int ret = -ENODEV;
#ifdef CONFIG_SH_MMCIF
gpio_request(GPIO_GP_4_31, NULL);
ret = mmcif_mmc_init();
#endif
+
+#ifdef CONFIG_SH_SDHI
+ gpio_request(GPIO_FN_SD0_DATA0, NULL);
+ gpio_request(GPIO_FN_SD0_DATA1, NULL);
+ gpio_request(GPIO_FN_SD0_DATA2, NULL);
+ gpio_request(GPIO_FN_SD0_DATA3, NULL);
+ gpio_request(GPIO_FN_SD0_CLK, NULL);
+ gpio_request(GPIO_FN_SD0_CMD, NULL);
+ gpio_request(GPIO_FN_SD0_CD, NULL);
+ gpio_request(GPIO_FN_SD1_DATA0, NULL);
+ gpio_request(GPIO_FN_SD1_DATA1, NULL);
+ gpio_request(GPIO_FN_SD1_DATA2, NULL);
+ gpio_request(GPIO_FN_SD1_DATA3, NULL);
+ gpio_request(GPIO_FN_SD1_CLK, NULL);
+ gpio_request(GPIO_FN_SD1_CMD, NULL);
+ gpio_request(GPIO_FN_SD1_CD, NULL);
+
+ /* SDHI 0 */
+ gpio_request(GPIO_GP_2_26, NULL);
+ gpio_request(GPIO_GP_2_29, NULL);
+ gpio_direction_output(GPIO_GP_2_26, 1);
+ gpio_direction_output(GPIO_GP_2_29, 1);
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+ SH_SDHI_QUIRK_16BIT_BUF);
+ if (ret)
+ return ret;
+
+ /* SDHI 1 */
+ gpio_request(GPIO_GP_4_26, NULL);
+ gpio_request(GPIO_GP_4_29, NULL);
+ gpio_direction_output(GPIO_GP_4_26, 1);
+ gpio_direction_output(GPIO_GP_4_29, 1);
+
+ ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
+#endif
return ret;
}
}
const struct rmobile_sysinfo sysinfo = {
- CONFIG_RMOBILE_BOARD_STRING
+ CONFIG_ARCH_RMOBILE_BOARD_STRING
};
void reset_cpu(ulong addr)