net: Move enetaddr env access code to env config instead of net config

[u-boot] / board / renesas / alt / alt.c

diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 523c5f131fa0330a699c20392da622f5a61a9028..f2200ef0810f0feba22bcbaac876503713298f89 100644 (file)
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -1,20 +1,26 @@
 /*
  * board/renesas/alt/alt.c
  *
- * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2014, 2015 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0
  */
 
 #include <common.h>
 #include <malloc.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <environment.h>
 #include <asm/processor.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
 #include <netdev.h>
 #include <miiphy.h>
 #include <i2c.h>
@@ -37,30 +43,16 @@ void s_init(void)
        qos_init();
 }
 
-#define MSTPSR1                0xE6150038
-#define SMSTPCR1       0xE6150134
 #define TMU0_MSTP125   (1 << 25)
-
-#define MSTPSR7                0xE61501C4
-#define SMSTPCR7       0xE615014C
 #define SCIF2_MSTP719  (1 << 19)
-
-#define MSTPSR8                0xE61509A0
-#define SMSTPCR8       0xE6150990
 #define ETHER_MSTP813  (1 << 13)
-
-#define MSTPSR3                0xE6150048
-#define SMSTPCR3       0xE615013C
 #define IIC1_MSTP323   (1 << 23)
+#define MMC0_MSTP315   (1 << 15)
+#define SDHI0_MSTP314  (1 << 14)
+#define SDHI1_MSTP312  (1 << 12)
 
-#define mstp_setbits(type, addr, saddr, set) \
-       out_##type((saddr), in_##type(addr) | (set))
-#define mstp_clrbits(type, addr, saddr, clear) \
-       out_##type((saddr), in_##type(addr) & ~(clear))
-#define mstp_setbits_le32(addr, saddr, set) \
-       mstp_setbits(le32, addr, saddr, set)
-#define mstp_clrbits_le32(addr, saddr, clear)   \
-       mstp_clrbits(le32, addr, saddr, clear)
+#define SD1CKCR                0xE6150078
+#define SD1_97500KHZ   0x7
 
 int board_early_init_f(void)
 {
@@ -76,13 +68,22 @@ int board_early_init_f(void)
        /* IIC1 / sh-i2c ch1 */
        mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
 
-       return 0;
-}
+#ifdef CONFIG_SH_MMCIF
+       /* MMC */
+       mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
+#endif
 
-void arch_preboot_os(void)
-{
-       /* Disable TMU0 */
-       mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+#ifdef CONFIG_SH_SDHI
+       /* SDHI0, 1 */
+       mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312);
+
+       /*
+        * SD0 clock is set to 97.5MHz by default.
+        * Set SD1 to the 97.5MHz as well.
+        */
+       writel(SD1_97500KHZ, SD1CKCR);
+#endif
+       return 0;
 }
 
 int board_init(void)
@@ -94,6 +95,20 @@ int board_init(void)
        r8a7794_pinmux_init();
 
        /* Ether Enable */
+#if defined(CONFIG_R8A7794_ETHERNET_B)
+       gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL);
+       gpio_request(GPIO_FN_ETH_RX_ER_B, NULL);
+       gpio_request(GPIO_FN_ETH_RXD0_B, NULL);
+       gpio_request(GPIO_FN_ETH_RXD1_B, NULL);
+       gpio_request(GPIO_FN_ETH_LINK_B, NULL);
+       gpio_request(GPIO_FN_ETH_REFCLK_B, NULL);
+       gpio_request(GPIO_FN_ETH_MDIO_B, NULL);
+       gpio_request(GPIO_FN_ETH_TXD1_B, NULL);
+       gpio_request(GPIO_FN_ETH_TX_EN_B, NULL);
+       gpio_request(GPIO_FN_ETH_MAGIC_B, NULL);
+       gpio_request(GPIO_FN_ETH_TXD0_B, NULL);
+       gpio_request(GPIO_FN_ETH_MDC_B, NULL);
+#else
        gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
        gpio_request(GPIO_FN_ETH_RX_ER, NULL);
        gpio_request(GPIO_FN_ETH_RXD0, NULL);
@@ -106,6 +121,7 @@ int board_init(void)
        gpio_request(GPIO_FN_ETH_MAGIC, NULL);
        gpio_request(GPIO_FN_ETH_TXD0, NULL);
        gpio_request(GPIO_FN_ETH_MDC, NULL);
+#endif
        gpio_request(GPIO_FN_IRQ8, NULL);
 
        /* PHY reset */
@@ -128,7 +144,7 @@ int board_eth_init(bd_t *bis)
        unsigned char enetaddr[6];
 
        ret = sh_eth_initialize(bis);
-       if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+       if (!eth_env_get_enetaddr("ethaddr", enetaddr))
                return ret;
 
        /* Set Mac address */
@@ -145,6 +161,55 @@ int board_eth_init(bd_t *bis)
 #endif
 }
 
+int board_mmc_init(bd_t *bis)
+{
+       int ret = -ENODEV;
+
+#ifdef CONFIG_SH_MMCIF
+       gpio_request(GPIO_GP_4_31, NULL);
+       gpio_set_value(GPIO_GP_4_31, 1);
+
+       ret = mmcif_mmc_init();
+#endif
+
+#ifdef CONFIG_SH_SDHI
+       gpio_request(GPIO_FN_SD0_DATA0, NULL);
+       gpio_request(GPIO_FN_SD0_DATA1, NULL);
+       gpio_request(GPIO_FN_SD0_DATA2, NULL);
+       gpio_request(GPIO_FN_SD0_DATA3, NULL);
+       gpio_request(GPIO_FN_SD0_CLK, NULL);
+       gpio_request(GPIO_FN_SD0_CMD, NULL);
+       gpio_request(GPIO_FN_SD0_CD, NULL);
+       gpio_request(GPIO_FN_SD1_DATA0, NULL);
+       gpio_request(GPIO_FN_SD1_DATA1, NULL);
+       gpio_request(GPIO_FN_SD1_DATA2, NULL);
+       gpio_request(GPIO_FN_SD1_DATA3, NULL);
+       gpio_request(GPIO_FN_SD1_CLK, NULL);
+       gpio_request(GPIO_FN_SD1_CMD, NULL);
+       gpio_request(GPIO_FN_SD1_CD, NULL);
+
+       /* SDHI 0 */
+       gpio_request(GPIO_GP_2_26, NULL);
+       gpio_request(GPIO_GP_2_29, NULL);
+       gpio_direction_output(GPIO_GP_2_26, 1);
+       gpio_direction_output(GPIO_GP_2_29, 1);
+
+       ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+                          SH_SDHI_QUIRK_16BIT_BUF);
+       if (ret)
+               return ret;
+
+       /* SDHI 1 */
+       gpio_request(GPIO_GP_4_26, NULL);
+       gpio_request(GPIO_GP_4_29, NULL);
+       gpio_direction_output(GPIO_GP_4_26, 1);
+       gpio_direction_output(GPIO_GP_4_29, 1);
+
+       ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0);
+#endif
+       return ret;
+}
+
 int dram_init(void)
 {
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
@@ -153,7 +218,7 @@ int dram_init(void)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-       CONFIG_RMOBILE_BOARD_STRING
+       CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 void reset_cpu(ulong addr)
@@ -165,3 +230,15 @@ void reset_cpu(ulong addr)
        val |= 0x02;
        i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 }
+
+static const struct sh_serial_platdata serial_platdata = {
+       .base = SCIF2_BASE,
+       .type = PORT_SCIF,
+       .clk = 14745600,
+       .clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(alt_serials) = {
+       .name = "serial_sh",
+       .platdata = &serial_platdata,
+};