Origen: Add default clock settings for multimedia IPs

[u-boot] / board / samsung / origen / lowlevel_init.S

diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index 928320120160a63fc1e18e7cdf0888ad000a1e48..9daa0da6143ec0051c181067d77b833c2a0407c8 100644 (file)
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -158,7 +158,22 @@ system_clock_init:
        ldr     r2, =CLK_SRC_PERIL0_OFFSET
        str     r1, [r0, r2]
 
-       /* FIMD0 */
+       /* CAM , FIMC 0-3 */
+       ldr     r1, =CLK_SRC_CAM_VAL
+       ldr     r2, =CLK_SRC_CAM_OFFSET
+       str     r1, [r0, r2]
+
+       /* MFC */
+       ldr     r1, =CLK_SRC_MFC_VAL
+       ldr     r2, =CLK_SRC_MFC_OFFSET
+       str     r1, [r0, r2]
+
+       /* G3D */
+       ldr     r1, =CLK_SRC_G3D_VAL
+       ldr     r2, =CLK_SRC_G3D_OFFSET
+       str     r1, [r0, r2]
+
+       /* LCD0 */
        ldr     r1, =CLK_SRC_LCD0_VAL
        ldr     r2, =CLK_SRC_LCD0_OFFSET
        str     r1, [r0, r2]
@@ -223,6 +238,26 @@ system_clock_init:
        ldr     r2, =CLK_DIV_PERIL0_OFFSET
        str     r1, [r0, r2]
 
+       /* CAM, FIMC 0-3: CAM Clock Divisors */
+       ldr     r1, =CLK_DIV_CAM_VAL
+       ldr     r2, =CLK_DIV_CAM_OFFSET
+       str     r1, [r0, r2]
+
+       /* CLK_DIV_MFC: MFC Clock Divisors */
+       ldr     r1, =CLK_DIV_MFC_VAL
+       ldr     r2, =CLK_DIV_MFC_OFFSET
+       str     r1, [r0, r2]
+
+       /* CLK_DIV_G3D: G3D Clock Divisors */
+       ldr     r1, =CLK_DIV_G3D_VAL
+       ldr     r2, =CLK_DIV_G3D_OFFSET
+       str     r1, [r0, r2]
+
+       /* CLK_DIV_LCD0: LCD0 Clock Divisors */
+       ldr     r1, =CLK_DIV_LCD0_VAL
+       ldr     r2, =CLK_DIV_LCD0_OFFSET
+       str     r1, [r0, r2]
+
        /* Set PLL locktime */
        ldr     r1, =PLL_LOCKTIME
        ldr     r2, =APLL_LOCK_OFFSET