]> git.sur5r.net Git - u-boot/blobdiff - board/samsung/smdk2410/smdk2410.c
SMDK2410: use the CFI driver (and remove the old one)
[u-boot] / board / samsung / smdk2410 / smdk2410.c
index 802348d23693f8ef25a4fe1299f3908848eb2df3..1abc4ba6a5041dc1069b8557e02b197590959507 100644 (file)
@@ -26,7 +26,8 @@
  */
 
 #include <common.h>
-#include <s3c2410.h>
+#include <netdev.h>
+#include <asm/arch/s3c24x0_cpu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -67,40 +68,41 @@ static inline void delay (unsigned long loops)
 
 int board_init (void)
 {
-       S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
-       S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+       struct s3c24x0_clock_power * const clk_power =
+                                       s3c24x0_get_base_clock_power();
+       struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
        /* to reduce PLL lock time, adjust the LOCKTIME register */
-       clk_power->LOCKTIME = 0xFFFFFF;
+       clk_power->locktime = 0xFFFFFF;
 
        /* configure MPLL */
-       clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+       clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
 
        /* some delay between MPLL and UPLL */
        delay (4000);
 
        /* configure UPLL */
-       clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+       clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
 
        /* some delay between MPLL and UPLL */
        delay (8000);
 
        /* set up the I/O ports */
-       gpio->GPACON = 0x007FFFFF;
-       gpio->GPBCON = 0x00044555;
-       gpio->GPBUP = 0x000007FF;
-       gpio->GPCCON = 0xAAAAAAAA;
-       gpio->GPCUP = 0x0000FFFF;
-       gpio->GPDCON = 0xAAAAAAAA;
-       gpio->GPDUP = 0x0000FFFF;
-       gpio->GPECON = 0xAAAAAAAA;
-       gpio->GPEUP = 0x0000FFFF;
-       gpio->GPFCON = 0x000055AA;
-       gpio->GPFUP = 0x000000FF;
-       gpio->GPGCON = 0xFF95FFBA;
-       gpio->GPGUP = 0x0000FFFF;
-       gpio->GPHCON = 0x002AFAAA;
-       gpio->GPHUP = 0x000007FF;
+       gpio->gpacon = 0x007FFFFF;
+       gpio->gpbcon = 0x00044555;
+       gpio->gpbup = 0x000007FF;
+       gpio->gpccon = 0xAAAAAAAA;
+       gpio->gpcup = 0x0000FFFF;
+       gpio->gpdcon = 0xAAAAAAAA;
+       gpio->gpdup = 0x0000FFFF;
+       gpio->gpecon = 0xAAAAAAAA;
+       gpio->gpeup = 0x0000FFFF;
+       gpio->gpfcon = 0x000055AA;
+       gpio->gpfup = 0x000000FF;
+       gpio->gpgcon = 0xFF95FFBA;
+       gpio->gpgup = 0x0000FFFF;
+       gpio->gphcon = 0x002AFAAA;
+       gpio->gphup = 0x000007FF;
 
        /* arch number of SMDK2410-Board */
        gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
@@ -121,3 +123,26 @@ int dram_init (void)
 
        return 0;
 }
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+       int rc = 0;
+#ifdef CONFIG_CS8900
+       rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
+#endif
+       return rc;
+}
+#endif
+
+/*
+ * Hardcoded flash setup:
+ * Flash 0 is a non-CFI AMD AM29LV800BB flash.
+ */
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+       info->portwidth = FLASH_CFI_16BIT;
+       info->chipwidth = FLASH_CFI_BY16;
+       info->interface = FLASH_CFI_X16;
+       return 1;
+}