* Copyright (c) 2005
* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
-#include "../common/ppc440gx_i2c.h"
#include "../common/sb_common.h"
+#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
+ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
+#include <net.h>
+#endif
void fpga_init (void);
ppc440_gpio_regs_t *gpio_regs;
/* Enable GPIO interrupts */
- mtsdr(sdr_pfc0, 0x00103E00);
+ mtsdr(SDR0_PFC0, 0x00103E00);
/* Setup access for LEDs, and system topology info */
gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
/*--------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------*/
- mtebc(xbcfg,
+ mtebc(EBC0_CFG,
EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
/*--------------------------------------------------------------------+
| 1/2 MB FLASH. Initialize bank 0 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb0ap,
+ mtebc(PB0AP,
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
- mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
+ mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
/*--------------------------------------------------------------------+
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb1ap,
+ mtebc(PB1AP,
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
- mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
+ mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
/*--------------------------------------------------------------------+
| Compact Flash, uses 2 Chip Selects (2 & 6)
+-------------------------------------------------------------------*/
- mtebc(pb2ap,
+ mtebc(PB2AP,
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
- mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
+ mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
/*--------------------------------------------------------------------+
| OPTO & OFEM FPGA. Initialize bank 3 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb3ap,
+ mtebc(PB3AP,
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
- mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
+ mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
| MAC A & B for Kamino. OFEM FPGA decodes the addresses
| Initialize bank 4 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb4ap,
+ mtebc(PB4AP,
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
- mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
+ mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
| Metrobox MAC B Initialize bank 5 with default values.
| KA REF FPGA Initialize bank 5 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb5ap,
+ mtebc(PB5AP,
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
- mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
+ mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
| Compact Flash, uses 2 Chip Selects (2 & 6)
+-------------------------------------------------------------------*/
- mtebc(pb6ap,
+ mtebc(PB6AP,
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
EBC_BXAP_PEN_DISABLED);
- mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
+ mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
/*--------------------------------------------------------------------+
| BME-32. Initialize bank 7 with default values.
+-------------------------------------------------------------------*/
- mtebc(pb7ap,
+ mtebc(PB7AP,
EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
- mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
+ mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
/*--------------------------------------------------------------------+
* UIC2 UIC1
* UIC3 UIC2
*/
- mtdcr (uic1sr, 0xffffffff); /* clear all */
- mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000000); /* all non- critical */
- mtdcr (uic1pr, 0xfffffe03); /* polarity */
- mtdcr (uic1tr, 0x01c00000); /* trigger edge vs level */
- mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
-
- mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uic2er, 0x00000000); /* disable all */
- mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffc8ff); /* polarity */
- mtdcr (uic2tr, 0x00ff0000); /* trigger edge vs level */
- mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic2sr, 0xffffffff); /* clear all */
-
- mtdcr (uic3sr, 0xffffffff); /* clear all */
- mtdcr (uic3er, 0x00000000); /* disable all */
- mtdcr (uic3cr, 0x00000000); /* all non-critical */
- mtdcr (uic3pr, 0xffff83ff); /* polarity */
- mtdcr (uic3tr, 0x00ff8c0f); /* trigger edge vs level */
- mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic3sr, 0xffffffff); /* clear all */
-
- mtdcr (uic0sr, 0xfc000000); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000000); /* all non-critical */
- mtdcr (uic0pr, 0xfc000000);
- mtdcr (uic0tr, 0x00000000);
- mtdcr (uic0vr, 0x00000001);
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+ mtdcr (UIC1ER, 0x00000000); /* disable all */
+ mtdcr (UIC1CR, 0x00000000); /* all non- critical */
+ mtdcr (UIC1PR, 0xfffffe03); /* polarity */
+ mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
+ mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+ mtdcr (UIC2ER, 0x00000000); /* disable all */
+ mtdcr (UIC2CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
+ mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
+ mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+ mtdcr (UIC3ER, 0x00000000); /* disable all */
+ mtdcr (UIC3CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC3PR, 0xffff83ff); /* polarity */
+ mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
+ mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr (UIC3SR, 0xffffffff); /* clear all */
+
+ mtdcr (UIC0SR, 0xfc000000); /* clear all */
+ mtdcr (UIC0ER, 0x00000000); /* disable all */
+ mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+ mtdcr (UIC0PR, 0xfc000000);
+ mtdcr (UIC0TR, 0x00000000);
+ mtdcr (UIC0VR, 0x00000001);
fpga_init();
************************************************************************/
int misc_init_f (void)
{
- /* Turn on i2c bus 1 */
- puts ("I2C1: ");
- i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- puts ("ready\n");
-
/* Turn on fans */
sbcommon_fans();
{
unsigned short sernum;
char envstr[255];
+ uchar enetaddr[6];
unsigned char opto_rev;
OPTO_FPGA_REGS_ST *opto_ps;
}
}
+#ifdef CONFIG_HAS_ETH0
+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+ board_get_enetaddr(0, enetaddr);
+ eth_setenv_enetaddr("ethaddr", enetaddr);
+ }
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+ if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+ board_get_enetaddr(1, enetaddr);
+ eth_setenv_enetaddr("eth1addr", enetaddr);
+ }
+#endif
+
+#ifdef CONFIG_HAS_ETH2
+ if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
+ board_get_enetaddr(2, enetaddr);
+ eth_setenv_enetaddr("eth2addr", enetaddr);
+ }
+#endif
+
+#ifdef CONFIG_HAS_ETH3
+ if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
+ board_get_enetaddr(3, enetaddr);
+ eth_setenv_enetaddr("eth3addr", enetaddr);
+ }
+#endif
+
return (0);
}
return;
}
-int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned short sernum;
char envstr[255];
return(1);
}
-int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned short sernum;
char envstr[255];
}
U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
- "Set environment to factory defaults", NULL);
+ "Set environment to factory defaults", "");
U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
- "Set environment to allow for fs recovery", NULL);
+ "Set environment to allow for fs recovery", "");
projects / u-boot / blobdiff