Align end of bss by 4 bytes

[u-boot] / board / sbc8548 / ddr.c

diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index f07d746c2054bf1c17ce68b7ec382dea198816dd..ab64fa88f2655916348963351f08d0e277fbc3f1 100644 (file)
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -10,6 +10,7 @@
 #include <i2c.h>
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
 static void
 get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
@@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd,
        }
 }
 
-void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num)
+void fsl_ddr_board_options(memctl_options_t *popts,
+                               dimm_params_t *pdimm,
+                               unsigned int ctrl_num)
 {
        /*
         * Factors to consider for clock adjust: