Merge branch 'master' of git://www.denx.de/git/u-boot-tq-group

[u-boot] / board / sbc8560 / sbc8560.c

diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index a784e3426a17400376374228f7aea1426a395b27..8df4f3a97538bfa498d5c935d40e44c2b51f64a0 100644 (file)
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -27,13 +27,11 @@
  */
 
 
-extern long int spd_sdram (void);
-
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <ioports.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
 
 long int fixed_sdram (void);
@@ -195,8 +193,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
-    volatile ccsr_pcix_t *pci = &immr->im_pcix;
+    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xfffffffdf; /* disable master abort */
 #endif
@@ -223,9 +220,14 @@ void reset_phy (void)
        udelay(1000);
 #endif
 #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
-       miiphy_reset(0x0);      /* reset PHY */
-       miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
-       miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+       /* reset PHY */
+       miiphy_reset("FCC1 ETHERNET", 0x0);
+
+       /* change PHY address to 0x02 */
+       bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
+
+       bb_miiphy_write(NULL, 0x02, PHY_BMCR,
+                       PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #endif /* CONFIG_MII */
 }
 
@@ -235,7 +237,11 @@ int checkboard (void)
 
        get_sys_info (&sysinfo);
 
+#ifdef CONFIG_SBC8560
        printf ("Board: Wind River SBC8560 Board\n");
+#else
+       printf ("Board: Wind River SBC8540 Board\n");
+#endif
        printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
        printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
        printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
@@ -254,15 +260,16 @@ int checkboard (void)
 long int initdram (int board_type)
 {
        long dram_size = 0;
-       extern long spd_sdram (void);
-       volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+#if 0
 #if !defined(CONFIG_RAM_AS_FLASH)
-       volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+       volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
        sys_info_t sysinfo;
        uint temp_lbcdll = 0;
 #endif
+#endif /* 0 */
 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
-       volatile ccsr_gur_t *gur= &immap->im_gur;
+       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_DDR_DLL)
        uint temp_ddrdll = 0;
@@ -279,7 +286,7 @@ long int initdram (int board_type)
        dram_size = fixed_sdram ();
 #endif
 
-#if XXX
+#if 0
 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
        get_sys_info(&sysinfo);
        /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
@@ -325,8 +332,7 @@ long int initdram (int board_type)
                 * enable errors */
                uint *p = 0;
                uint i = 0;
-               volatile immap_t *immap = (immap_t *)CFG_IMMR;
-               volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+               volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
                dma_init();
                for (*p = 0; p < (uint *)(8 * 1024); p++) {
                        if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -413,8 +419,7 @@ long int fixed_sdram (void)
 #define CFG_DDR_CONTROL 0xc2000000
 
   #ifndef CFG_RAMBOOT
-       volatile immap_t *immap = (immap_t *)CFG_IMMR;
-       volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+       volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
 
        ddr->cs0_bnds           = 0x00000007;
        ddr->cs1_bnds           = 0x0010001f;