ppc/85xx: 32bit DDR changes for P1020/P1011

[u-boot] / board / sbc8560 / sbc8560.c

diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index 413926d1f53e0f8cbdcf7242a2e5dbd39c1580d4..c40b5e38ddd89b0c3d2bfd828a98b7653a0a96dc 100644 (file)
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -238,6 +238,7 @@ void reset_phy (void)
 int checkboard (void)
 {
        sys_info_t sysinfo;
+       char buf[32];
 
        get_sys_info (&sysinfo);
 
@@ -246,16 +247,17 @@ int checkboard (void)
 #else
        printf ("Board: Wind River SBC8540 Board\n");
 #endif
-       printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
-       printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
-       printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+       printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
+       printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
+       printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
        if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
                || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
-               printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CONFIG_SYS_LBC_LCRR & 0x0f));
+               printf ("\tLBC: %s MHz\n",
+                       strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
        } else {
                printf("\tLBC: unknown\n");
        }
-       printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+       printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
        printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
        return (0);
 }
@@ -295,7 +297,7 @@ phys_size_t initdram (int board_type)
 #if 0
 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
        get_sys_info(&sysinfo);
-       /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+       /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
        if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
                lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
        } else {
@@ -336,40 +338,9 @@ phys_size_t initdram (int board_type)
        {
                /* Initialize all of memory for ECC, then
                 * enable errors */
-               uint *p = 0;
-               uint i = 0;
                volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-               dma_init();
-               for (*p = 0; p < (uint *)(8 * 1024); p++) {
-                       if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
-                       *p = (unsigned int)0xdeadbeef;
-                       if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
-               }
 
-               /* 8K */
-               dma_xfer((uint *)0x2000,0x2000,(uint *)0);
-               /* 16K */
-               dma_xfer((uint *)0x4000,0x4000,(uint *)0);
-               /* 32K */
-               dma_xfer((uint *)0x8000,0x8000,(uint *)0);
-               /* 64K */
-               dma_xfer((uint *)0x10000,0x10000,(uint *)0);
-               /* 128k */
-               dma_xfer((uint *)0x20000,0x20000,(uint *)0);
-               /* 256k */
-               dma_xfer((uint *)0x40000,0x40000,(uint *)0);
-               /* 512k */
-               dma_xfer((uint *)0x80000,0x80000,(uint *)0);
-               /* 1M */
-               dma_xfer((uint *)0x100000,0x100000,(uint *)0);
-               /* 2M */
-               dma_xfer((uint *)0x200000,0x200000,(uint *)0);
-               /* 4M */
-               dma_xfer((uint *)0x400000,0x400000,(uint *)0);
-
-               for (i = 1; i < dram_size / 0x800000; i++) {
-                       dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
-               }
+               dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
 
                /* Enable errors for ECC */
                ddr->err_disable = 0x00000000;