#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
-#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc (unsigned int dram_size);
-#endif
-
long int fixed_sdram (void);
int board_early_init_f (void)
return dram_size;
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc (dram_size);
-#endif
-
puts (" DDR: ");
return dram_size;
}
ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
- ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
udelay (500);
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B;
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
asm ("sync; isync");
udelay (500);
ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A;
+ ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
- ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1;
+ ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
udelay (500);
- ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B;
+ ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
asm ("sync; isync");
udelay (500);
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
+ struct pci_region *r = hose->regions;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
debug("\n");
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI1_MEM_BASE,
+ pci_set_region(r++,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI1_IO_BASE,
+ pci_set_region(r++,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
- fsl_pci_init(hose);
+ fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno=hose->last_busno+1;
printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
#ifdef CONFIG_PCI2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
+ struct pci_region *r = hose->regions;
/* inbound */
- pci_set_region(hose->regions + 0,
- CONFIG_SYS_PCI_MEMORY_BUS,
- CONFIG_SYS_PCI_MEMORY_PHYS,
- CONFIG_SYS_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
- pci_set_region(hose->regions + 1,
- CONFIG_SYS_PCI2_MEM_BASE,
+ pci_set_region(r++,
+ CONFIG_SYS_PCI2_MEM_BUS,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
- pci_set_region(hose->regions + 2,
- CONFIG_SYS_PCI2_IO_BASE,
+ pci_set_region(r++,
+ CONFIG_SYS_PCI2_IO_BUS,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
- hose->region_count = 3;
+ hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
- fsl_pci_init(hose);
+ fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
first_free_busno=hose->last_busno+1;
printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
#if defined(CONFIG_OF_BOARD_SETUP)
-
-void
-ft_board_setup (void *blob, bd_t *bd)
+void ft_board_setup (void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
- }
}
#endif
return val;
}
+
+void board_reset(void)
+{
+#ifdef CONFIG_SYS_RESET_ADDRESS
+ ulong addr = CONFIG_SYS_RESET_ADDRESS;
+
+ /* flush and disable I/D cache */
+ __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
+ __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
+ __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
+ __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 4");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+ __asm__ __volatile__ ("mtspr 1008, 5");
+ __asm__ __volatile__ ("isync");
+ __asm__ __volatile__ ("sync");
+
+ /*
+ * SRR0 has system reset vector, SRR1 has default MSR value
+ * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
+ */
+ __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
+ __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
+ __asm__ __volatile__ ("mtspr 27, 4");
+ __asm__ __volatile__ ("rfi");
+#endif
+}
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
projects / u-boot / blobdiff