static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
- struct nand_chip *this = mtd->priv;
- if (ctrl & NAND_CTRL_CHANGE) {
+ struct nand_chip *this = mtd->priv;
+ if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
set_bit (SC3_NAND_CLE, sc3_control_base);
else
clear_bit (SC3_NAND_CE, sc3_control_base);
}
- if (cmd != NAND_CMD_NONE)
+ if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
{
nand->ecc.mode = NAND_ECC_SOFT;
- sc3_io_base = (void *) CFG_NAND_BASE;
+ sc3_io_base = (void *) CONFIG_SYS_NAND_BASE;
/* Set address of NAND IO lines (Using Linear Data Access Region) */
nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
nand->IO_ADDR_W = (void __iomem *) sc3_io_base;