#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
+#include <linux/compiler.h>
#include "scm.h"
+DECLARE_GLOBAL_DATA_PTR;
+
static void config_scoh_cs(void);
extern int fpga_init(void);
/* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */
/* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */
/* PB18 */ { 0, 1, 0, 0, 0, 0 },
- /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
- /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
- /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
- /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
- /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
- /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
- /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
- /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
- /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
- /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
- /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
- /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
- /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
- /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
+ /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
+ /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
+ /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
+ /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
+ /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
+ /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
+ /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
+ /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
+ /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
+ /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
+ /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
+ /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
+ /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
+ /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
/* PC19 */ { 0, 1, 0, 0, 0, 0 },
/* PC18 */ { 0, 1, 0, 0, 0, 0 },
- /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
- /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
+ /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
+ /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
/* PC15 */ { 0, 0, 0, 1, 0, 0 },
/* PC14 */ { 0, 1, 0, 0, 0, 0 },
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */
*/
int checkboard (void)
{
- unsigned char str[64];
- int i = getenv_r ("serial#", str, sizeof (str));
+ char str[64];
+ int i = getenv_f("serial#", str, sizeof (str));
puts ("Board: ");
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
- ulong cnt, val;
- volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
+ ulong maxsize, size;
int i;
- ulong save[32]; /* to make test non-destructive */
- ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
*/
maxsize = (1 + (~orx | 0x7fff)) / 2;
- /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+ /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
* we are configuring CS1 if base != 0
*/
sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
+ *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
- /*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
- i = 0;
- for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- save[i++] = *addr;
- *addr = ~cnt;
- }
+ size = get_ram_size((long *)base, maxsize);
- addr = (volatile ulong *) base;
- save[i] = *addr;
- *addr = 0;
+ *orx_ptr = orx | ~(size - 1);
- if ((val = *addr) != 0) {
- *addr = save[i];
- return (0);
- }
-
- for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
- addr = (volatile ulong *) base + cnt; /* pointer arith! */
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
- /* Write the actual size to ORx
- */
- *orx_ptr = orx | ~(cnt * sizeof (long) - 1);
- return (cnt * sizeof (long));
- }
- }
- return (maxsize);
+ return (size);
}
/*
*/
int power_on_reset (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* Test Reset Status Register */
return gd->reset_status & RSR_CSRS ? 0 : 1;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
long size8, size9;
#endif
long psize, lsize;
psize = 16 * 1024 * 1024;
lsize = 0;
- memctl->memc_psrt = CFG_PSRT;
- memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_psrt = CONFIG_SYS_PSRT;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
#if 0 /* Just for debugging */
#define prt_br_or(brX,orX) do { \
ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
printf ("\n" \
- #brX " 0x%08x " #orX " 0x%08x " \
+ #brX " 0x%08x " #orX " 0x%08x " \
"==> 0x%08lx ... 0x%08lx = %ld MB\n", \
memctl->memc_ ## brX, memctl->memc_ ## orX, \
start, start+sizem, (sizem+1)>>20); \
prt_br_or (br3, or3);
#endif
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
/* 60x SDRAM setup:
*/
- size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
- (uchar *) CFG_SDRAM_BASE);
- size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
- (uchar *) CFG_SDRAM_BASE);
+ size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+ size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL - %ld MB, ", psize >> 20);
} else {
- psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
- (uchar *) CFG_SDRAM_BASE);
+ psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
printf ("(60x:8COL - %ld MB, ", psize >> 20);
}
/* Local SDRAM setup:
*/
-#ifdef CFG_INIT_LOCAL_SDRAM
- memctl->memc_lsrt = CFG_LSRT;
- size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
+ memctl->memc_lsrt = CONFIG_SYS_LSRT;
+ size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
(uchar *) SDRAM_BASE2_PRELIM);
- size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
+ size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
(uchar *) SDRAM_BASE2_PRELIM);
if (size8 < size9) {
lsize = size9;
printf ("Local:9COL - %ld MB) using ", lsize >> 20);
} else {
- lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+ lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
(uchar *) SDRAM_BASE2_PRELIM);
printf ("Local:8COL - %ld MB) using ", lsize >> 20);
}
/* Set up BR2 so that the local SDRAM goes
* right after the 60x SDRAM
*/
- memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
- (CFG_SDRAM_BASE + psize);
+ memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
+ (CONFIG_SYS_SDRAM_BASE + psize);
#endif
-#endif /* CFG_INIT_LOCAL_SDRAM */
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
+#endif /* CONFIG_SYS_RAMBOOT */
icache_enable ();
static void config_scoh_cs (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immr->im_memctl;
- volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE;
- volatile uint tmp, i;
+ volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE;
+ __maybe_unused volatile uint tmp, i;
/* Initialize OR3 / BR3 for CAN Bus Controller 0 */
- memctl->memc_or3 = CFG_CAN0_OR3;
- memctl->memc_br3 = CFG_CAN0_BR3;
+ memctl->memc_or3 = CONFIG_SYS_CAN0_OR3;
+ memctl->memc_br3 = CONFIG_SYS_CAN0_BR3;
/* Initialize OR4 / BR4 for CAN Bus Controller 1 */
- memctl->memc_or4 = CFG_CAN1_OR4;
- memctl->memc_br4 = CFG_CAN1_BR4;
+ memctl->memc_or4 = CONFIG_SYS_CAN1_OR4;
+ memctl->memc_br4 = CONFIG_SYS_CAN1_BR4;
/* Initialize MAMR to write in the array at address 0x0 */
memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
/* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
- memctl->memc_or5 = CFG_EXTPROM_OR5;
- memctl->memc_br5 = CFG_EXTPROM_BR5;
+ memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5;
+ memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5;
/* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
- memctl->memc_or6 = CFG_EXTPROM_OR6;
- memctl->memc_br6 = CFG_EXTPROM_BR6;
+ memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6;
+ memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6;
/* Initialize OR7 / BR7 for the Glue Logic */
- memctl->memc_or7 = CFG_FIOX_OR7;
- memctl->memc_br7 = CFG_FIOX_BR7;
+ memctl->memc_or7 = CONFIG_SYS_FIOX_OR7;
+ memctl->memc_br7 = CONFIG_SYS_FIOX_BR7;
/* Initialize OR8 / BR8 for the DOH Logic */
- memctl->memc_or8 = CFG_FDOHM_OR8;
- memctl->memc_br8 = CFG_FDOHM_BR8;
+ memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8;
+ memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8;
DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
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