#include <common.h>
#include <config.h>
+#include <jffs2/jffs2.h>
#include <mpc8xx.h>
#include <net.h> /* for eth_init() */
#include <rtc.h>
# include <status_led.h>
#endif
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#include <linux/mtd/nand.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+#endif
+
#define ORMASK(size) ((-size) & OR_AM_MSK)
static long ram_size(ulong *, long);
/* write program data to FPGA at the programming address
* so extra /CS1 strobes at end of configuration don't actually
- * write to any registers.
+ * write to any registers.
*/
fpga = 0xff; /* first write is ignored */
fpga = 0xff; /* fill byte */
return (0);
}
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_init(void)
+{
+ unsigned long totlen = nand_probe(CFG_DFLASH_BASE);
+
+ printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
/* ------------------------------------------------------------------------- */
/*
ramsize = 0; /* no RAM present, or defective */
else {
*base_addr = 0xaaaa5555;
- *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
+ *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
if (*base_addr != 0xaaaa5555)
ramsize = 0; /* no RAM present, or defective */
}
_not_used_, _not_used_, _not_used_, _not_used_,
/* single write. (offset 18 in upm RAM) */
- /* FADS had 0x1f27fc04, ...
+ /* FADS had 0x1f27fc04, ...
* but most other boards have 0x1f07fc04, which
* sets GPL0 from A11MPC to 0 1/4 clock earlier,
* like the single read.
* This may be too fast, but works for any memory.
* It is adjusted to 4096 cycles in 64 milliseconds if
* possible once we know what memory we have.
- *
+ *
* We have to be careful changing UPM registers after we
* ask it to run these commands.
*
* SCCR[DFBRG] 0
* PTP divide by 8
* 1 chip select
- */
+ */
memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
return (size_sdram);
}
-