#include <common.h>
#include <config.h>
+#include <jffs2/jffs2.h>
#include <mpc8xx.h>
#include <net.h> /* for eth_init() */
#include <rtc.h>
#include "sixnet.h"
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
#define ORMASK(size) ((-size) & OR_AM_MSK)
/* ------------------------------------------------------------------------- */
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+void show_boot_progress (int status)
+{
+#if defined(CONFIG_STATUS_LED)
+# if defined(STATUS_LED_BOOT)
+ if (status == 15) {
+ /* ready to transfer to kernel, make sure LED is proper state */
+ status_led_set(STATUS_LED_BOOT, CONFIG_BOOT_LED_STATE);
+ }
+# endif /* STATUS_LED_BOOT */
+#endif /* CONFIG_STATUS_LED */
+}
+#endif
+
+/* ------------------------------------------------------------------------- */
+
/*
* Check Board Identity:
* returns 0 if recognized, -1 if unknown
/* ------------------------------------------------------------------------- */
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#if defined(CONFIG_CMD_PCMCIA)
#error "SXNI855T has no PCMCIA port"
-#endif /* CFG_CMD_PCMCIA */
+#endif
/* ------------------------------------------------------------------------- */
#define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
#define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
#define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
-#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */
+#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */
int board_postclk_init (void)
{
# include "fpgadata.c"
};
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
#define porta (immap->im_ioport.iop_padat)
const unsigned char* pdata;
/* write program data to FPGA at the programming address
* so extra /CS1 strobes at end of configuration don't actually
- * write to any registers.
+ * write to any registers.
*/
fpga = 0xff; /* first write is ignored */
fpga = 0xff; /* fill byte */
/* ------------------------------------------------------------------------- */
/* base address for SRAM, assume 32-bit port, valid */
-#define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V)
+#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
/* up to 64MB - will be adjusted for actual size */
-#define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \
+#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \
| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
/*
* Miscellaneous platform dependent initializations after running in RAM.
int misc_init_r (void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
bd_t *bd = gd->bd;
+ uchar enetaddr[6];
memctl->memc_or2 = NVRAM_OR_PRELIM;
memctl->memc_br2 = NVRAM_BR_VALUE;
/* Is there any SRAM? Is it 16 or 32 bits wide? */
/* First look for 32-bit SRAM */
- bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+ bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
if (bd->bi_sramsize == 0) {
/* no 32-bit SRAM, but there could be 16-bit SRAM since
* Try again with a 16-bit bus.
*/
memctl->memc_br2 |= BR_PS_16;
- bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+ bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
}
if (bd->bi_sramsize == 0) {
else {
/* adjust or2 for actual size of SRAM */
memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
- bd->bi_sramstart = CFG_SRAM_BASE;
+ bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
}
immap->im_sit.sit_rtc = tim;
}
-#if 0
- /* The code below is no longer valid since the prototype of
- * eth_init() and eth_halt() have been changed to support
- * multi-ethernet feature in U-Boot; the eth_initialize()
- * routine should be called before any access to the ethernet
- * callbacks.
+ /* set up ethernet address for SCC ethernet. If eth1addr
+ * is present it gets a unique address, otherwise it
+ * shares the FEC address.
*/
+ if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
+ eth_getenv_enetaddr("ethaddr", enetaddr);
+ eth_setenv_enetaddr("eth1addr", enetaddr);
+ }
- /* FIXME - for now init ethernet to force PHY special mode */
- eth_init(bd);
- eth_halt();
-#endif
return (0);
}
+#if defined(CONFIG_CMD_NAND)
+void nand_init(void)
+{
+ unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
+
+ printf ("%4lu MB\n", totlen >> 20);
+}
+#endif
+
/* ------------------------------------------------------------------------- */
/*
*
* The memory size MUST be a power of 2 for this to work.
*
- * The only memory modified is 4 bytes at offset 0. This is important
+ * The only memory modified is 8 bytes at offset 0. This is important
* since for the SRAM this location is reserved for autosizing, so if
* it is modified and the board is reset before ram_size() completes
* no damage is done. Normally even the memory at 0 is preserved. The
static long ram_size(ulong *base, long maxsize)
{
volatile long *test_addr;
- volatile long *base_addr = base;
- volatile long *flash = (volatile long*)CFG_FLASH_BASE;
+ volatile ulong *base_addr = base;
ulong ofs; /* byte offset from base_addr */
ulong save; /* to make test non-destructive */
- ulong junk;
+ ulong save2; /* to make test non-destructive */
long ramsize = -1; /* size not determined yet */
save = *base_addr; /* save value at 0 so can restore */
+ save2 = *(base_addr+1); /* save value at 4 so can restore */
/* is any SRAM present? */
*base_addr = 0x5555aaaa;
- /* use flash read to modify data bus, since with no SRAM present
- * the data bus may retain the value if our code is running
- * completely in the cache.
+ /* It is important to drive the data bus with different data so
+ * it doesn't remember the value and look like RAM that isn't there.
*/
- junk = *flash;
+ *(base_addr + 1) = 0xaaaa5555; /* use write to modify data bus */
if (*base_addr != 0x5555aaaa)
ramsize = 0; /* no RAM present, or defective */
else {
*base_addr = 0xaaaa5555;
- junk = *flash; /* use flash read to modify data bus */
+ *(base_addr + 1) = 0x5555aaaa; /* use write to modify data bus */
if (*base_addr != 0xaaaa5555)
ramsize = 0; /* no RAM present, or defective */
}
}
*base_addr = save; /* restore value at 0 */
+ *(base_addr+1) = save2; /* restore value at 4 */
return (ramsize);
}
_not_used_, _not_used_, _not_used_, _not_used_,
/* single write. (offset 18 in upm RAM) */
- /* FADS had 0x1f27fc04, ...
+ /* FADS had 0x1f27fc04, ...
* but most other boards have 0x1f07fc04, which
* sets GPL0 from A11MPC to 0 1/4 clock earlier,
* like the single read.
MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
/* MAMR values work in either mamr or mbmr */
-/* 8 column SDRAM */
-#define SDRAM_MAMR_8COL /* refresh at 50MHz */ \
+#define SDRAM_MAMR_BASE /* refresh at 50MHz */ \
((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
- | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
| MAMR_DSA_1_CYCL /* 1 cycle disable */ \
- | MAMR_G0CLA_A11 /* GPL0 A11[MPC] */ \
| MAMR_RLFA_1X /* Read loop 1 time */ \
| MAMR_WLFA_1X /* Write loop 1 time */ \
| MAMR_TLFA_4X) /* Timer loop 4 times */
+/* 8 column SDRAM */
+#define SDRAM_MAMR_8COL (SDRAM_MAMR_BASE \
+ | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
+ | MAMR_G0CLA_A11) /* GPL0 A11[MPC] */
/* 9 column SDRAM */
-#define SDRAM_MAMR_9COL ((SDRAM_MAMR_8COL & (~MAMR_G0CLA_A11)) | MAMR_G0CLA_A10)
+#define SDRAM_MAMR_9COL (SDRAM_MAMR_BASE \
+ | MAMR_AMA_TYPE_1 /* Address MUX 1 */ \
+ | MAMR_G0CLA_A10) /* GPL0 A10[MPC] */
/* base address 0, 32-bit port, SDRAM UPM, valid */
#define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
/* ------------------------------------------------------------------------- */
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
uint size_sdram = 0;
uint size_sdram9 = 0;
* This may be too fast, but works for any memory.
* It is adjusted to 4096 cycles in 64 milliseconds if
* possible once we know what memory we have.
- *
+ *
* We have to be careful changing UPM registers after we
* ask it to run these commands.
*
* SCCR[DFBRG] 0
* PTP divide by 8
* 1 chip select
- */
+ */
memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
return (size_sdram);
}
-
projects / u-boot / blobdiff