fsl-ddr: use the 1T timing as default configuration

[u-boot] / board / stxgp3 / Makefile

diff --git a/board/stxgp3/Makefile b/board/stxgp3/Makefile
index 28d6cb9976e01b39caea1008c3d46629242f5b7e..5a68f11e7d0506bdcebbbddfa3a4c9cd95b07820 100644 (file)
--- a/board/stxgp3/Makefile
+++ b/board/stxgp3/Makefile
@@ -25,10 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).a
 
-COBJS  := $(BOARD).o flash.o law.o tlb.o
-
-SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
+COBJS-y        += $(BOARD).o
+COBJS-y        += law.o
+COBJS-y        += tlb.o
+COBJS-y        += flash.o
+COBJS-$(CONFIG_FSL_DDR1) += ddr.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
 SOBJS  := $(addprefix $(obj),$(SOBJS))
 
 $(LIB):        $(obj).depend $(OBJS) $(SOBJS)
@@ -38,7 +42,7 @@ clean:
        rm -f $(OBJS) $(SOBJS)
 
 distclean:     clean
-       rm -f $(LIB) core *.bak .depend
+       rm -f $(LIB) core *.bak $(obj).depend
 
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