86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields

[u-boot] / board / stxssa / stxssa.c

diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c
index 5882124150e49dc479e300e21483ff87a2c0be8e..73dddf3e0c94822da588e6d0832fa9d0904089e9 100644 (file)
--- a/board/stxssa/stxssa.c
+++ b/board/stxssa/stxssa.c
@@ -29,16 +29,17 @@
  */
 
 
-extern long int spd_sdram (void);
-
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
+#include <asm/mmu.h>
 #include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
 #include <ioports.h>
 #include <asm/io.h>
-#include <spd.h>
+#include <spd_sdram.h>
 #include <miiphy.h>
+#include <netdev.h>
 
 long int fixed_sdram (void);
 
@@ -206,7 +207,7 @@ reset_phy(void)
 #if 0
        int     i;
 #endif
-       blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE;
+       blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
 
        /* reset Giga bit Ethernet port if needed here */
 
@@ -252,8 +253,7 @@ int
 board_early_init_f(void)
 {
 #if defined(CONFIG_PCI)
-       volatile immap_t *immr = (immap_t *)CFG_IMMR;
-       volatile ccsr_pcix_t *pci = &immr->im_pcix;
+       volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
 
        pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -284,7 +284,7 @@ show_activity(int flag)
        if (next_led_update > get_ticks())
                return;
 
-       blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE;
+       blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
 
        led_bit >>= 1;
        if (led_bit == 0)
@@ -294,16 +294,14 @@ show_activity(int flag)
        next_led_update += (get_tbclk() / 4);
 }
 
-long int
+phys_size_t
 initdram (int board_type)
 {
        long dram_size = 0;
-       extern long spd_sdram (void);
 
 #if defined(CONFIG_DDR_DLL)
        {
-               volatile immap_t *immap = (immap_t *)CFG_IMMR;
-               volatile ccsr_gur_t *gur= &immap->im_gur;
+               volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
                uint temp_ddrdll = 0;
 
                /* Work around to stabilize DDR DLL */
@@ -313,7 +311,9 @@ initdram (int board_type)
        }
 #endif
 
-       dram_size = spd_sdram ();
+       dram_size = fsl_ddr_sdram();
+       dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+       dram_size *= 0x100000;
 
 #if defined(CONFIG_DDR_ECC)
        /* Initialize and enable DDR ECC.
@@ -325,11 +325,11 @@ initdram (int board_type)
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-       uint *pstart = (uint *) CFG_MEMTEST_START;
-       uint *pend = (uint *) CFG_MEMTEST_END;
+       uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+       uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
        uint *p;
 
        printf("SDRAM test phase 1:\n");
@@ -378,9 +378,14 @@ static struct pci_config_table pci_stxgp3_config_table[] = {
 #endif
 
 
-static struct pci_controller hose = {
+static struct pci_controller hose[] = {
 #ifndef CONFIG_PCI_PNP
-       config_table: pci_stxgp3_config_table,
+       { config_table: pci_stxgp3_config_table,},
+#else
+       {},
+#endif
+#ifdef CONFIG_MPC85XX_PCI2
+       {},
 #endif
 };
 
@@ -393,6 +398,12 @@ pci_init_board(void)
 #ifdef CONFIG_PCI
        extern void pci_mpc85xx_init(struct pci_controller *hose);
 
-       pci_mpc85xx_init(&hose);
+       pci_mpc85xx_init(hose);
 #endif /* CONFIG_PCI */
 }
+
+int board_eth_init(bd_t *bis)
+{
+       cpu_eth_init(bis);      /* Initialize TSECs first */
+       return pci_eth_init(bis);
+}