if ARCH_SUNXI
+config IDENT_STRING
+ default " Allwinner Technology"
+
+# FIXME: Should not redefine these Kconfig symbols
+config PRE_CONSOLE_BUFFER
+ default y
+
+config SPL_GPIO_SUPPORT
+ default y
+
+config SPL_LIBCOMMON_SUPPORT
+ default y
+
+config SPL_LIBDISK_SUPPORT
+ default y
+
+config SPL_LIBGENERIC_SUPPORT
+ default y
+
+config SPL_MMC_SUPPORT
+ depends on SPL && GENERIC_MMC
+ default y
+
+config SPL_POWER_SUPPORT
+ default y
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+config SUNXI_HIGH_SRAM
+ bool
+ default n
+ ---help---
+ Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
+ with the first SRAM region being located at address 0.
+ Some newer SoCs map the boot ROM at address 0 instead and move the
+ SRAM to 64KB, just behind the mask ROM.
+ Chips using the latter setup are supposed to select this option to
+ adjust the addresses accordingly.
+
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig
config SUNXI_GEN_SUN4I
watchdog, etc.
+config MACH_SUNXI_H3_H5
+ bool
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
choice
prompt "Sunxi SoC Variant"
optional
config MACH_SUN4I
bool "sun4i (Allwinner A10)"
select CPU_V7
+ select ARM_CORTEX_CPU_IS_UP
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
config MACH_SUN5I
bool "sun5i (Allwinner A13)"
select CPU_V7
+ select ARM_CORTEX_CPU_IS_UP
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN4I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
select CPU_V7
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+config MACH_SUN8I_A83T
+ bool "sun8i (Allwinner A83T)"
+ select CPU_V7
+ select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
+config MACH_SUN8I_H3
+ bool "sun8i (Allwinner H3)"
+ select CPU_V7
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
+ select MACH_SUNXI_H3_H5
+ select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+
config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
+ select SUNXI_HIGH_SRAM
select SUNXI_GEN_SUN6I
+ select SUPPORT_SPL
+
+config MACH_SUN50I
+ bool "sun50i (Allwinner A64)"
+ select ARM64
+ select SUNXI_GEN_SUN6I
+ select SUNXI_HIGH_SRAM
+ select SUPPORT_SPL
+
+config MACH_SUN50I_H5
+ bool "sun50i (Allwinner H5)"
+ select ARM64
+ select MACH_SUNXI_H3_H5
+ select SUNXI_HIGH_SRAM
endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
config MACH_SUN8I
bool
- default y if MACH_SUN8I_A23 || MACH_SUN8I_A33
+ default y if MACH_SUN8I_A23
+ default y if MACH_SUN8I_A33
+ default y if MACH_SUN8I_A83T
+ default y if MACH_SUNXI_H3_H5
+
+config RESERVE_ALLWINNER_BOOT0_HEADER
+ bool "reserve space for Allwinner boot0 header"
+ select ENABLE_ARM_SOC_BOOT0_HOOK
+ ---help---
+ Prepend a 1536 byte (empty) header to the U-Boot image file, to be
+ filled with magic values post build. The Allwinner provided boot0
+ blob relies on this information to load and execute U-Boot.
+ Only needed on 64-bit Allwinner boards so far when using boot0.
+config ARM_BOOT_HOOK_RMR
+ bool
+ depends on ARM64
+ default y
+ select ENABLE_ARM_SOC_BOOT0_HOOK
+ ---help---
+ Insert some ARM32 code at the very beginning of the U-Boot binary
+ which uses an RMR register write to bring the core into AArch64 mode.
+ The very first instruction acts as a switch, since it's carefully
+ chosen to be a NOP in one mode and a branch in the other, so the
+ code would only be executed if not already in AArch64.
+ This allows both the SPL and the U-Boot proper to be entered in
+ either mode and switch to AArch64 if needed.
+
+config DRAM_TYPE
+ int "sunxi dram type"
+ depends on MACH_SUN8I_A83T
+ default 3
+ ---help---
+ Set the dram type, 3: DDR3, 7: LPDDR3
config DRAM_CLK
int "sunxi dram clock speed"
+ default 792 if MACH_SUN9I
default 312 if MACH_SUN6I || MACH_SUN8I
default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+ default 672 if MACH_SUN50I
---help---
- Set the dram clock speed, valid range 240 - 480, must be a multiple
- of 24.
+ Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
+ must be a multiple of 24. For the sun9i (A80), the tested values
+ (for DDR3-1600) are 312 to 792.
if MACH_SUN5I || MACH_SUN7I
config DRAM_MBUS_CLK
int "sunxi dram zq value"
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
+ default 4145117 if MACH_SUN9I
+ default 3881915 if MACH_SUN50I
---help---
Set the dram zq value.
bool "sunxi dram odt enable"
default n if !MACH_SUN8I_A23
default y if MACH_SUN8I_A23
+ default y if MACH_SUN50I
---help---
Select this to enable dram odt (on die termination).
endif
config SYS_CLK_FREQ
+ default 1008000000 if MACH_SUN4I
+ default 1008000000 if MACH_SUN5I
+ default 1008000000 if MACH_SUN6I
default 912000000 if MACH_SUN7I
- default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
+ default 1008000000 if MACH_SUN8I
+ default 1008000000 if MACH_SUN9I
+ default 816000000 if MACH_SUN50I
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
default "sun7i" if MACH_SUN7I
default "sun8i" if MACH_SUN8I
default "sun9i" if MACH_SUN9I
+ default "sun50i" if MACH_SUN50I
config SYS_BOARD
default "sunxi"
Only enable this if you really know what you are doing.
config OLD_SUNXI_KERNEL_COMPAT
- boolean "Enable workarounds for booting old kernels"
+ bool "Enable workarounds for booting old kernels"
default n
---help---
Set this to enable various workarounds for old kernels, this results in
sub-optimal settings for newer kernels, only enable if needed.
-config MMC
- depends on !UART0_PORT_F
- default y if ARCH_SUNXI
+config MACPWR
+ string "MAC power pin"
+ default ""
+ help
+ Set the pin used to power the MAC. This takes a string in the format
+ understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config MMC0_CD_PIN
string "Card detect pin for mmc0"
+ default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
default ""
---help---
Set the card detect pin for mmc0, leave empty to not use cd. This
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
+config INITIAL_USB_SCAN_DELAY
+ int "delay initial usb scan by x ms to allow builtin devices to init"
+ default 0
+ ---help---
+ Some boards have on board usb devices which need longer than the
+ USB spec's 1 second to connect from board powerup. Set this config
+ option to a non 0 value to add an extra delay before the first usb
+ bus scan.
+
config USB0_VBUS_PIN
string "Vbus enable pin for usb0 (otg)"
default ""
---help---
See USB1_VBUS_PIN help text.
+config USB3_VBUS_PIN
+ string "Vbus enable pin for usb3 (ehci2)"
+ default ""
+ ---help---
+ See USB1_VBUS_PIN help text.
+
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default n if MACH_SUN6I || MACH_SUN8I
+ select CMD_I2C
---help---
This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
its clock and setting up the bus. This is especially useful on devices
config I2C1_ENABLE
bool "Enable I2C/TWI controller 1"
default n
+ select CMD_I2C
---help---
See I2C0_ENABLE help text.
config I2C2_ENABLE
bool "Enable I2C/TWI controller 2"
default n
+ select CMD_I2C
---help---
See I2C0_ENABLE help text.
config I2C3_ENABLE
bool "Enable I2C/TWI controller 3"
default n
+ select CMD_I2C
---help---
See I2C0_ENABLE help text.
endif
+if SUNXI_GEN_SUN6I
+config R_I2C_ENABLE
+ bool "Enable the PRCM I2C/TWI controller"
+ # This is used for the pmic on H3
+ default y if SY8106A_POWER
+ select CMD_I2C
+ ---help---
+ Set this to y to enable the I2C controller which is part of the PRCM.
+endif
+
if MACH_SUN7I
config I2C4_ENABLE
bool "Enable I2C/TWI controller 4"
default n
+ select CMD_I2C
---help---
See I2C0_ENABLE help text.
endif
config AXP_GPIO
- boolean "Enable support for gpio-s on axp PMICs"
+ bool "Enable support for gpio-s on axp PMICs"
default n
---help---
Say Y here to enable support for the gpio pins of the axp PMIC ICs.
config VIDEO
- boolean "Enable graphical uboot console on HDMI, LCD or VGA"
+ bool "Enable graphical uboot console on HDMI, LCD or VGA"
+ depends on !MACH_SUN8I_A83T
+ depends on !MACH_SUNXI_H3_H5
+ depends on !MACH_SUN9I
+ depends on !MACH_SUN50I
default y
---help---
Say Y here to add support for using a cfb console on the HDMI, LCD
info on how to select the video output and mode.
config VIDEO_HDMI
- boolean "HDMI output support"
+ bool "HDMI output support"
depends on VIDEO && !MACH_SUN8I
default y
---help---
Say Y here to add support for outputting video over HDMI.
config VIDEO_VGA
- boolean "VGA output support"
+ bool "VGA output support"
depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
default n
---help---
Say Y here to add support for outputting video over VGA.
config VIDEO_VGA_VIA_LCD
- boolean "VGA via LCD controller support"
+ bool "VGA via LCD controller support"
depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
default n
---help---
Olimex A13 boards.
config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
- boolean "Force sync active high for VGA via LCD controller support"
+ bool "Force sync active high for VGA via LCD controller support"
depends on VIDEO_VGA_VIA_LCD
default n
---help---
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
config VIDEO_COMPOSITE
- boolean "Composite video output support"
+ bool "Composite video output support"
depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
default n
---help---
bool "LCD panel needs to be configured via i2c"
depends on VIDEO
default n
+ select CMD_I2C
---help---
Say y here if the LCD panel needs to be configured via i2c. This
will add a bitbang i2c controller using gpios to talk to the LCD.
endchoice
+config SATAPWR
+ string "SATA power pin"
+ default ""
+ help
+ Set the pins used to power the SATA. This takes a string in the
+ format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
+ port H.
config GMAC_TX_DELAY
int "GMAC Transmit Clock Delay Chain"
Set the GMAC Transmit Clock Delay Chain value.
config SPL_STACK_R_ADDR
- default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I
+ default 0x4fe00000 if MACH_SUN4I
+ default 0x4fe00000 if MACH_SUN5I
+ default 0x4fe00000 if MACH_SUN6I
+ default 0x4fe00000 if MACH_SUN7I
+ default 0x4fe00000 if MACH_SUN8I
default 0x2fe00000 if MACH_SUN9I
+ default 0x4fe00000 if MACH_SUN50I
endif
projects / u-boot / blobdiff