SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / board / tbs / tbs2910 / tbs2910.c

diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index daf8ff4e6218b633942131bb20adfd90a6a4f6ca..ecb45f208d0c2a72be0468c01830525b9962aa69 100644 (file)
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -1,20 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/sata.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
@@ -219,15 +218,13 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
-       s32 status = 0;
-       int i;
-
        /*
-        * (U-boot device node)    (Physical Port)
+        * (U-Boot device node)    (Physical Port)
         * mmc0                    SD2
         * mmc1                    SD3
         * mmc2                    eMMC
         */
+       int i, ret;
        for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
                switch (i) {
                case 0:
@@ -251,12 +248,24 @@ int board_mmc_init(bd_t *bis)
                        printf("Warning: you configured more USDHC controllers"
                               "(%d) then supported by the board (%d)\n",
                               i + 1, CONFIG_SYS_FSL_USDHC_NUM);
-                       return status;
+                       return -EINVAL;
                }
-
-               status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+               ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+               if (ret)
+                       return ret;
        }
-       return status;
+       return 0;
+}
+
+/* set environment device to boot device when booting from SD */
+int board_mmc_get_env_dev(int devno)
+{
+       return devno - 1;
+}
+
+int board_mmc_get_env_part(int devno)
+{
+       return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
 }
 #endif /* CONFIG_FSL_ESDHC */
 
@@ -327,24 +336,61 @@ static void setup_display(void)
        reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
        writel(reg, &ccm->analog_pll_video);
 
-       /* select video pll for ldb_di0_clk */
-       reg = readl(&ccm->cs2cdr);
-       reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
-       writel(reg, &ccm->cs2cdr);
-
-       /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
-       reg = readl(&ccm->cscmr2);
-       reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
-       writel(reg, &ccm->cscmr2);
+       /* gate ipu1_di0_clk */
+       reg = readl(&ccm->CCGR3);
+       reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
+       writel(reg, &ccm->CCGR3);
 
-       /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */
+       /* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
        reg = readl(&ccm->chsccdr);
-       reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-               << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+       reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
+                MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
+                MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+       reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
+              (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
+              (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
        writel(reg, &ccm->chsccdr);
+
+       /* enable ipu1_di0_clk */
+       reg = readl(&ccm->CCGR3);
+       reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
+       writel(reg, &ccm->CCGR3);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
+static int ar8035_phy_fixup(struct phy_device *phydev)
+{
+       unsigned short val;
+
+       /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+       val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+       val &= 0xffe3;
+       val |= 0x18;
+       phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+       /* introduce tx clock delay */
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+       val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+       val |= 0x0100;
+       phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+       return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+       ar8035_phy_fixup(phydev);
+
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
+
+       return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
        setup_iomux_enet();
@@ -364,11 +410,17 @@ static const struct boot_mode board_boot_modes[] = {
        {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
        {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
        /* 8 bit bus width */
-       {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+       {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
        {NULL,   0},
 };
 #endif
 
+#ifdef CONFIG_USB_EHCI_MX6
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+       MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
 int board_init(void)
 {
        /* address of boot parameters */
@@ -387,6 +439,10 @@ int board_init(void)
 #endif
 #ifdef CONFIG_CMD_BMODE
        add_board_boot_modes(board_boot_modes);
+#endif
+#ifdef CONFIG_USB_EHCI_MX6
+       imx_iomux_v3_setup_multiple_pads(
+               usb_otg_pads, ARRAY_SIZE(usb_otg_pads));
 #endif
        return 0;
 }