*
* Copyright (C) 2009 TechNexion Ltd.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/omap_gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/dss.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <i2c.h>
#include <spartan3.h>
#include <asm/gpio.h>
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
static struct panel_config lcd_cfg[] = {
{
- .timing_h = PANEL_TIMING_H(4, 8, 41),
- .timing_v = PANEL_TIMING_V(2, 4, 10),
- .pol_freq = 0x00000000, /* Pol Freq */
- .divisor = 0x0001000d, /* 33Mhz Pixel Clock */
+ .timing_h = PANEL_TIMING_H(40, 5, 2),
+ .timing_v = PANEL_TIMING_V(8, 8, 2),
+ .pol_freq = 0x00003000, /* Pol Freq */
+ .divisor = 0x00010033, /* 9 Mhz Pixel Clock */
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = 0,
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
},
{
.timing_h = PANEL_TIMING_H(20, 192, 4),
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = 0,
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
}
};
#endif
FPGA_GPMC_CONFIG6,
};
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+ return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(int index)
{
debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__);
- fpga_reset(TRUE);
+ fpga_reset(true);
udelay(100);
- fpga_reset(FALSE);
+ fpga_reset(false);
return 0;
}
return assert_clk;
}
-Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = {
+xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = {
fpga_pre_config_fn,
fpga_pgm_fn,
fpga_clk_fn,
fpga_post_config_fn,
};
-Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
+xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial,
(void *)&mt_ventoux_fpga_fns, 0);
/* Initialize the FPGA */
return 0;
}
+#ifndef CONFIG_SPL_BUILD
int misc_init_r(void)
{
char *eth_addr;
+ struct tam3517_module_info info;
+ int ret;
- dieid_num_r();
+ TAM3517_READ_EEPROM(&info, ret);
+ omap_die_id_display();
- eth_addr = getenv("ethaddr");
- if (eth_addr)
+ if (ret)
return 0;
+ eth_addr = getenv("ethaddr");
+ if (!eth_addr)
+ TAM3517_READ_MAC_FROM_EEPROM(&info);
-#ifndef CONFIG_SPL_BUILD
- TAM3517_READ_MAC_FROM_EEPROM;
-#endif
+ TAM3517_PRINT_SOM_INFO(&info);
return 0;
}
+#endif
/*
* Routine: set_muxconf_regs
return 0;
}
-#if defined(CONFIG_OMAP_HSMMC) && \
+#if defined(CONFIG_MMC_OMAP_HS) && \
!defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0);
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif