am43xx: Tune the system to avoid DSS underflows

[u-boot] / board / ti / am43xx / board.c

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index 5eaa4a554b9153f741e2427c4308cfa0e861772d..7e239f1c88ab29f32a538ba05424fa337f412259 100644 (file)
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -157,12 +157,16 @@ const struct emif_regs emif_regs_lpddr2 = {
        .emif_rd_wr_lvl_rmp_ctl         = 0x0,
        .emif_rd_wr_lvl_ctl             = 0x0,
        .emif_ddr_phy_ctlr_1            = 0x0E084006,
-       .emif_rd_wr_exec_thresh         = 0x00000405,
+       .emif_rd_wr_exec_thresh         = 0x80000405,
        .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
        .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
        .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
        .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00500050
+       .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                        = 0x000FFFFF
 };
 
 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
@@ -217,7 +221,11 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
        .emif_rd_wr_lvl_rmp_win         = 0x0,
        .emif_rd_wr_lvl_rmp_ctl         = 0x0,
        .emif_rd_wr_lvl_ctl             = 0x0,
-       .emif_rd_wr_exec_thresh         = 0x00000405
+       .emif_rd_wr_exec_thresh         = 0x80000405,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                = 0x000FFFFF
 };
 
 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
@@ -236,7 +244,11 @@ const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
        .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
        .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
        .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
-       .emif_rd_wr_exec_thresh         = 0x00000405
+       .emif_rd_wr_exec_thresh         = 0x80000405,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                = 0x000FFFFF
 };
 
 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
@@ -255,7 +267,11 @@ const struct emif_regs ddr3_emif_regs_400Mhz_production = {
        .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
        .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
        .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
-       .emif_rd_wr_exec_thresh         = 0x00000405
+       .emif_rd_wr_exec_thresh         = 0x80000405,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                = 0x000FFFFF
 };
 
 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
@@ -277,7 +293,11 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
        .emif_rd_wr_lvl_rmp_win         = 0x0,
        .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
-       .emif_rd_wr_exec_thresh         = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x80000000,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                = 0x000FFFFF
 };
 
 const u32 ext_phy_ctrl_const_base_ddr3[] = {
@@ -587,8 +607,44 @@ void sdram_init(void)
 
 int board_init(void)
 {
+       struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
+       u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
+           modena_init0_bw_integer, modena_init0_watermark_0;
+
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+       /* Clear all important bits for DSS errata that may need to be tweaked*/
+       mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
+                          MREQPRIO_0_SAB_INIT0_MASK;
+
+       mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
+
+       modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
+                                          BW_LIMITER_BW_FRAC_MASK;
+
+       modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
+                                       BW_LIMITER_BW_INT_MASK;
+
+       modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
+                                        BW_LIMITER_BW_WATERMARK_MASK;
+
+       /* Setting MReq Priority of the DSS*/
+       mreqprio_0 |= 0x77;
+
+       /*
+        * Set L3 Fast Configuration Register
+        * Limiting bandwith for ARM core to 700 MBPS
+        */
+       modena_init0_bw_fractional |= 0x10;
+       modena_init0_bw_integer |= 0x3;
+
+       writel(mreqprio_0, &cdev->mreqprio_0);
+       writel(mreqprio_1, &cdev->mreqprio_1);
+
+       writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
+       writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
+       writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
+
        return 0;
 }