#include <asm/gpio.h>
#include <usb.h>
#include <linux/usb/gadget.h>
+#include <asm/omap_common.h>
+#include <asm/omap_sec_common.h>
#include <asm/arch/gpio.h>
#include <asm/arch/dra7xx_iodelay.h>
#include <asm/emif.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <ti-usb-phy-uboot.h>
+#include <miiphy.h>
#include "mux_data.h"
#include "../common/board_detect.h"
#define board_is_dra74x_evm() board_ti_is("5777xCPU")
+#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
(strncmp("H", board_ti_get_rev(), 1) <= 0)
+#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() && \
+ (strncmp("C", board_ti_get_rev(), 1) <= 0)
#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
board_ti_get_emif2_size()
.emif_rd_wr_exec_thresh = 0x00000305
};
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
+ .sdram_config_init = 0x61862BB2,
+ .sdram_config = 0x61862BB2,
+ .sdram_config2 = 0x00000000,
+ .ref_ctrl = 0x0000514D,
+ .ref_ctrl_final = 0x0000144A,
+ .sdram_tim1 = 0xD1137824,
+ .sdram_tim2 = 0x30B37FE3,
+ .sdram_tim3 = 0x409F8AD8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x5007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0824400E,
+ .emif_ddr_phy_ctlr_1 = 0x0E24400E,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
+ .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
+ .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
+ .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x00000305
+};
+
const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
}
break;
case DRA722_ES1_0:
- *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+ case DRA722_ES2_0:
+ if (ram_size < CONFIG_MAX_MEM_MAPPED)
+ *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+ else
+ *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
break;
default:
*regs = &emif1_ddr3_532_mhz_1cs;
.is_ma_present = 0x1
};
+/*
+ * DRA722 EVM EMIF1 2GB CONFIGURATION
+ * EMIF1 4 devices of 512Mb x 8 Micron
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x80700100,
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
u64 ram_size;
*dmm_lisa_regs = &lisa_map_dra7_1536MB;
break;
case DRA722_ES1_0:
+ case DRA722_ES2_0:
default:
- *dmm_lisa_regs = &lisa_map_2G_x_2;
+ if (ram_size < CONFIG_MAX_MEM_MAPPED)
+ *dmm_lisa_regs = &lisa_map_2G_x_2;
+ else
+ *dmm_lisa_regs = &lisa_map_2G_x_4;
+ break;
}
}
+struct vcores_data dra752_volts = {
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS659038_REG_ADDR_SMPS12,
+ .mpu.pmic = &tps659038,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS659038_REG_ADDR_SMPS45,
+ .eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS659038_REG_ADDR_SMPS6,
+ .gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS659038_REG_ADDR_SMPS7,
+ .core.pmic = &tps659038,
+
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS659038_REG_ADDR_SMPS8,
+ .iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
+struct vcores_data dra722_volts = {
+ .mpu.value = VDD_MPU_DRA7,
+ .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
+ .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .mpu.addr = TPS65917_REG_ADDR_SMPS1,
+ .mpu.pmic = &tps659038,
+ .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+
+ .core.value = VDD_CORE_DRA7,
+ .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
+ .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .core.addr = TPS65917_REG_ADDR_SMPS2,
+ .core.pmic = &tps659038,
+
+ /*
+ * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
+ * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
+ */
+ .gpu.value = VDD_GPU_DRA7,
+ .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
+ .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .gpu.addr = TPS65917_REG_ADDR_SMPS3,
+ .gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
+
+ .eve.value = VDD_EVE_DRA7,
+ .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
+ .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .eve.addr = TPS65917_REG_ADDR_SMPS3,
+ .eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
+
+ .iva.value = VDD_IVA_DRA7,
+ .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
+ .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+ .iva.addr = TPS65917_REG_ADDR_SMPS3,
+ .iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
+};
+
/**
* @brief board_init
*
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char *name = "unknown";
- if (is_dra72x())
- name = "dra72x";
- else
+ if (is_dra72x()) {
+ if (board_is_dra72x_revc_or_later())
+ name = "dra72x-revc";
+ else
+ name = "dra72x";
+ } else {
name = "dra7xx";
+ }
set_board_info_env(name);
if (board_is_dra74x_evm()) {
bname = "DRA74x EVM";
- /* If EEPROM is not populated */
+ } else if (board_is_dra72x_evm()) {
+ bname = "DRA72x EVM";
} else {
+ /* If EEPROM is not populated */
if (is_dra72x())
bname = "DRA72x EVM";
else
}
#endif /* CONFIG_SPL_BUILD */
+void vcores_init(void)
+{
+ if (board_is_dra74x_evm()) {
+ *omap_vcores = &dra752_volts;
+ } else if (board_is_dra72x_evm()) {
+ *omap_vcores = &dra722_volts;
+ } else {
+ /* If EEPROM is not populated */
+ if (is_dra72x())
+ *omap_vcores = &dra722_volts;
+ else
+ *omap_vcores = &dra752_volts;
+ }
+}
+
void set_muxconf_regs(void)
{
do_set_mux32((*ctrl)->control_padconf_core_base,
#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
- struct pad_conf_entry const *pads;
+ struct pad_conf_entry const *pads, *delta_pads = NULL;
struct iodelay_cfg_entry const *iodelay;
- int npads, niodelays;
+ int npads, niodelays, delta_npads = 0;
+ int ret;
switch (omap_revision()) {
case DRA722_ES1_0:
- pads = dra72x_core_padconf_array;
- npads = ARRAY_SIZE(dra72x_core_padconf_array);
- iodelay = dra72_iodelay_cfg_array;
- niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array);
+ case DRA722_ES2_0:
+ pads = dra72x_core_padconf_array_common;
+ npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
+ if (board_is_dra72x_revc_or_later()) {
+ delta_pads = dra72x_rgmii_padconf_array_revc;
+ delta_npads =
+ ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
+ iodelay = dra72_iodelay_cfg_array_revc;
+ niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
+ } else {
+ delta_pads = dra72x_rgmii_padconf_array_revb;
+ delta_npads =
+ ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
+ iodelay = dra72_iodelay_cfg_array_revb;
+ niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
+ }
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
RGMII1_ID_MODE_N_MASK);
break;
}
- __recalibrate_iodelay(pads, npads, iodelay, niodelays);
+ /* Setup I/O isolation */
+ ret = __recalibrate_iodelay_start();
+ if (ret)
+ goto err;
+
+ /* Do the muxing here */
+ do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
+
+ /* Now do the weird minor deltas that should be safe */
+ if (delta_npads)
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ delta_pads, delta_npads);
+
+ /* Setup IOdelay configuration */
+ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
+err:
+ /* Closeup.. remove isolation */
+ __recalibrate_iodelay_end(ret);
}
#endif
if (*omap_si_rev == DRA722_ES1_0)
cpsw_data.active_slave = 1;
+ if (board_is_dra72x_revc_or_later()) {
+ cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
+ cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
+ }
+
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
return;
/* Do not enable VTT for DRA722 */
- if (omap_revision() == DRA722_ES1_0)
+ if (is_dra72x())
return;
/*
return 0;
}
#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (is_dra72x()) {
+ if (board_is_dra72x_revc_or_later()) {
+ if (!strcmp(name, "dra72-evm-revc"))
+ return 0;
+ } else if (!strcmp(name, "dra72-evm")) {
+ return 0;
+ }
+ } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
+ return 0;
+ }
+
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+void board_fit_image_post_process(void **p_image, size_t *p_size)
+{
+ secure_boot_verify_image(p_image, p_size);
+}
+#endif
projects / u-boot / blobdiff