/*
- * (C) Copyright 2004-2008
+ * (C) Copyright 2004-2011
* Texas Instruments, <www.ti.com>
*
* Author :
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
#include <i2c.h>
#include <asm/mach-types.h>
+#include <linux/mtd/nand.h>
#include "evm.h"
#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank. This
+ * provides the timing values back to the function that configures
+ * the memory.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ int pop_mfr, pop_id;
+
+ /*
+ * We need to identify what PoP memory is on the board so that
+ * we know what timings to use. To map the ID values please see
+ * nand_ids.c
+ */
+ identify_nand_chip(&pop_mfr, &pop_id);
+
+ if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
+ /* 256MB DDR */
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ } else {
+ /* 128MB DDR */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ }
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ timings->mr = MICRON_V_MR_165;
+}
+#endif
+
/*
* Routine: misc_init_r
* Description: Init ethernet (done here so udelay works)
rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
}
- ret = omap_request_gpio(rst_gpio);
+ ret = gpio_request(rst_gpio, "");
if (ret < 0) {
printf("Unable to get GPIO %d\n", rst_gpio);
return ;
}
/* Configure as output */
- omap_set_gpio_direction(rst_gpio, 0);
+ gpio_direction_output(rst_gpio, 0);
/* Send a pulse on the GPIO pin */
- omap_set_gpio_dataout(rst_gpio, 1);
+ gpio_set_value(rst_gpio, 1);
udelay(1);
- omap_set_gpio_dataout(rst_gpio, 0);
+ gpio_set_value(rst_gpio, 0);
udelay(1);
- omap_set_gpio_dataout(rst_gpio, 1);
+ gpio_set_value(rst_gpio, 1);
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR "ethaddr"
+
+ struct eth_device *dev;
+ uchar eth_addr[6];
+
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+
+ if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+ dev = eth_get_dev_by_index(0);
+ if (dev) {
+ eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+ } else {
+ printf("omap3evm: Couldn't get eth device\n");
+ rc = -1;
+ }
+ }
#endif
return rc;
}
#endif /* CONFIG_CMD_NET */
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif