arm: dts: Add devicetree for i.MX6Q

[u-boot] / board / ti / ks2_evm / board.c

diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index ff7bc4bb18d695feac087803a04ad37a881a1430..03254e1497684e263d175f7558c80de5b4389d5f 100644 (file)
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -7,18 +7,20 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
-#include "board.h"
 #include <common.h>
+#include "board.h"
 #include <spl.h>
 #include <exports.h>
 #include <fdt_support.h>
 #include <asm/arch/ddr3.h>
 #include <asm/arch/psc_defs.h>
+#include <asm/arch/clock.h>
 #include <asm/ti-common/ti-aemif.h>
 #include <asm/ti-common/keystone_net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TI_AEMIF)
 static struct aemif_config aemif_configs[] = {
        {                       /* CS0 */
                .mode           = AEMIF_MODE_NAND,
@@ -32,26 +34,37 @@ static struct aemif_config aemif_configs[] = {
                .width          = AEMIF_WIDTH_8,
        },
 };
+#endif
 
 int dram_init(void)
 {
-       ddr3_init();
+       u32 ddr3_size;
+
+       ddr3_size = ddr3_init();
 
        gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
                                    CONFIG_MAX_RAM_BANK_SIZE);
+#if defined(CONFIG_TI_AEMIF)
        aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
-       ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE);
+#endif
+
+       if (ddr3_size)
+               ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+       else
+               ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, gd->ram_size >> 30);
+
        return 0;
 }
 
 int board_init(void)
 {
-       gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR;
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
        return 0;
 }
 
 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+#ifndef CONFIG_DM_ETH
 int get_eth_env_param(char *env_name)
 {
        char *env;
@@ -71,14 +84,21 @@ int board_eth_init(bd_t *bis)
        int port_num;
        char link_type_name[32];
 
+       if (cpu_is_k2g())
+               writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
+
        /* By default, select PA PLL clock as PA clock source */
+#ifndef CONFIG_SOC_K2G
        if (psc_enable_module(KS2_LPSC_PA))
                return -1;
+#endif
        if (psc_enable_module(KS2_LPSC_CPGMAC))
                return -1;
        if (psc_enable_module(KS2_LPSC_CRYPTO))
                return -1;
-       pass_pll_pa_clk_enable();
+
+       if (cpu_is_k2e() || cpu_is_k2l())
+               pll_pa_clk_sel();
 
        port_num = get_num_eth_ports();
 
@@ -94,6 +114,7 @@ int board_eth_init(bd_t *bis)
        return 0;
 }
 #endif
+#endif
 
 #ifdef CONFIG_SPL_BUILD
 void spl_board_init(void)
@@ -113,8 +134,8 @@ u32 spl_boot_device(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
 {
        int lpae;
        char *env;
@@ -133,9 +154,7 @@ void ft_board_setup(void *blob, bd_t *bd)
 
        ddr3a_size = 0;
        if (lpae) {
-               env = getenv("ddr3a_size");
-               if (env)
-                       ddr3a_size = simple_strtol(env, NULL, 10);
+               ddr3a_size = ddr3_get_size();
                if ((ddr3a_size != 8) && (ddr3a_size != 4))
                        ddr3a_size = 0;
        }
@@ -217,6 +236,8 @@ void ft_board_setup(void *blob, bd_t *bd)
                        }
                }
        }
+
+       return 0;
 }
 
 void ft_board_setup_ex(void *blob, bd_t *bd)
@@ -255,4 +276,4 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
 
        ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */