]> git.sur5r.net Git - u-boot/blobdiff - board/ti/ks2_evm/board.c
env: Rename setenv() to env_set()
[u-boot] / board / ti / ks2_evm / board.c
index e16669da081fdcafbeea24068e0bd67ebc2cc91b..c61baeeb8cf5d76093160db0408caf48120a71fe 100644 (file)
@@ -20,6 +20,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TI_AEMIF)
 static struct aemif_config aemif_configs[] = {
        {                       /* CS0 */
                .mode           = AEMIF_MODE_NAND,
@@ -33,6 +34,7 @@ static struct aemif_config aemif_configs[] = {
                .width          = AEMIF_WIDTH_8,
        },
 };
+#endif
 
 int dram_init(void)
 {
@@ -42,9 +44,19 @@ int dram_init(void)
 
        gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
                                    CONFIG_MAX_RAM_BANK_SIZE);
-       aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
-       if (ddr3_size)
-               ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+#if defined(CONFIG_TI_AEMIF)
+       if (!board_is_k2g_ice())
+               aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
+#endif
+
+       if (!board_is_k2g_ice()) {
+               if (ddr3_size)
+                       ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+               else
+                       ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
+                                     gd->ram_size >> 30);
+       }
+
        return 0;
 }
 
@@ -126,7 +138,7 @@ u32 spl_boot_device(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
        int lpae;
@@ -268,4 +280,11 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
 
        ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 }
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+#if defined(CONFIG_DTB_RESELECT)
+int __weak embedded_dtb_select(void)
+{
+       return 0;
+}
 #endif