configs: x86: allow to override CONFIG_BOOTCOMMAND

[u-boot] / board / ti / ks2_evm / board_k2e.c

diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index 2043759533021c03ad80141a0e2161d77d89645b..6c77d915e5b977c1f3fac3b2dbeaf366fec89a2e 100644 (file)
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -14,17 +14,30 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-unsigned int external_clk[ext_clk_count] = {
-       [sys_clk]       = 100000000,
-       [alt_core_clk]  = 100000000,
-       [pa_clk]        = 100000000,
-       [ddr3_clk]      = 100000000,
-       [mcm_clk]       = 312500000,
-       [pcie_clk]      = 100000000,
-       [sgmii_clk]     = 156250000,
-       [xgmii_clk]     = 156250000,
-       [usb_clk]       = 100000000,
-};
+unsigned int get_external_clk(u32 clk)
+{
+       unsigned int clk_freq;
+
+       switch (clk) {
+       case sys_clk:
+               clk_freq = 100000000;
+               break;
+       case alt_core_clk:
+               clk_freq = 100000000;
+               break;
+       case pa_clk:
+               clk_freq = 100000000;
+               break;
+       case ddr3a_clk:
+               clk_freq = 100000000;
+               break;
+       default:
+               clk_freq = 0;
+               break;
+       }
+
+       return clk_freq;
+}
 
 static struct pll_init_data core_pll_config[NUM_SPDS] = {
        [SPD800]        = CORE_PLL_800,
@@ -59,6 +72,26 @@ s16 divn_val[16] = {
 static struct pll_init_data pa_pll_config =
        PASS_PLL_1000;
 
+struct pll_init_data *get_pll_init_data(int pll)
+{
+       int speed;
+       struct pll_init_data *data;
+
+       switch (pll) {
+       case MAIN_PLL:
+               speed = get_max_dev_speed(speeds);
+               data = &core_pll_config[speed];
+               break;
+       case PASS_PLL:
+               data = &pa_pll_config;
+               break;
+       default:
+               data = NULL;
+       }
+
+       return data;
+}
+
 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
 struct eth_priv_t eth_priv_cfg[] = {
        {
@@ -67,6 +100,7 @@ struct eth_priv_t eth_priv_cfg[] = {
                .phy_addr        = 0,
                .slave_port      = 1,
                .sgmii_link_type = SGMII_LINK_MAC_PHY,
+               .phy_if          = PHY_INTERFACE_MODE_SGMII,
        },
        {
                .int_name        = "K2E_EMAC1",
@@ -74,6 +108,7 @@ struct eth_priv_t eth_priv_cfg[] = {
                .phy_addr        = 1,
                .slave_port      = 2,
                .sgmii_link_type = SGMII_LINK_MAC_PHY,
+               .phy_if          = PHY_INTERFACE_MODE_SGMII,
        },
        {
                .int_name        = "K2E_EMAC2",
@@ -81,6 +116,7 @@ struct eth_priv_t eth_priv_cfg[] = {
                .phy_addr        = 2,
                .slave_port      = 3,
                .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+               .phy_if          = PHY_INTERFACE_MODE_SGMII,
        },
        {
                .int_name        = "K2E_EMAC3",
@@ -88,6 +124,7 @@ struct eth_priv_t eth_priv_cfg[] = {
                .phy_addr        = 3,
                .slave_port      = 4,
                .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+               .phy_if          = PHY_INTERFACE_MODE_SGMII,
        },
        {
                .int_name        = "K2E_EMAC4",
@@ -95,6 +132,7 @@ struct eth_priv_t eth_priv_cfg[] = {
                .phy_addr        = 4,
                .slave_port      = 5,
                .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+               .phy_if          = PHY_INTERFACE_MODE_SGMII,
        },
        {
                .int_name        = "K2E_EMAC5",
@@ -102,6 +140,7 @@ struct eth_priv_t eth_priv_cfg[] = {
                .phy_addr        = 5,
                .slave_port      = 6,
                .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+               .phy_if          = PHY_INTERFACE_MODE_SGMII,
        },
        {
                .int_name        = "K2E_EMAC6",
@@ -109,6 +148,7 @@ struct eth_priv_t eth_priv_cfg[] = {
                .phy_addr        = 6,
                .slave_port      = 7,
                .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+               .phy_if          = PHY_INTERFACE_MODE_SGMII,
        },
        {
                .int_name        = "K2E_EMAC7",
@@ -116,6 +156,7 @@ struct eth_priv_t eth_priv_cfg[] = {
                .phy_addr        = 7,
                .slave_port      = 8,
                .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+               .phy_if          = PHY_INTERFACE_MODE_SGMII,
        },
 };
 
@@ -125,27 +166,28 @@ int get_num_eth_ports(void)
 }
 #endif
 
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void)
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
 {
-       int speed;
+       if (!strcmp(name, "keystone-k2e-evm"))
+               return 0;
 
-       speed = get_max_dev_speed();
-       init_pll(&core_pll_config[speed]);
+       return -1;
+}
+#endif
 
-       init_pll(&pa_pll_config);
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+int board_early_init_f(void)
+{
+       init_plls();
 
        return 0;
 }
 #endif
 
 #ifdef CONFIG_SPL_BUILD
-static struct pll_init_data spl_pll_config[] = {
-       CORE_PLL_800,
-};
-
 void spl_init_keystone_plls(void)
 {
-       init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
+       init_plls();
 }
 #endif