PCIe, USB: Replace 'end point' references with 'endpoint'

[u-boot] / board / tqc / tqm85xx / nand.c

diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
index dea652dfd9fab0d4acff5661720b61d9fc182cb1..3da689a9e46ffb3105f1129735032c8c2c785d32 100644 (file)
--- a/board/tqc/tqm85xx/nand.c
+++ b/board/tqc/tqm85xx/nand.c
@@ -385,7 +385,7 @@ static void upmb_write (u_char addr, ulong val)
                        MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
 
        /* dummy access to perform write */
-       out_8 ((void __iomem *)CONFIG_SYS_NAND0_BASE, 0);
+       out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0);
 
        clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
 }
@@ -395,7 +395,7 @@ static void upmb_write (u_char addr, ulong val)
  */
 static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
 {
-       uint i;
+       uint i, j;
        uint or3 = CONFIG_SYS_OR3_PRELIM;
        uint clock = get_lbc_clock ();
 
@@ -429,8 +429,8 @@ static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
        /* Assign address of table */
        nand_upm_patt = upm_freq_table[i].upm_patt;
 
-       for (i = 0; i < 64; i++) {
-               upmb_write (i, *nand_upm_patt);
+       for (j = 0; j < 64; j++) {
+               upmb_write (j, *nand_upm_patt);
                nand_upm_patt++;
        }
 
@@ -446,7 +446,10 @@ static struct fsl_upm_nand fun = {
        .width = 8,
        .upm_cmd_offset = 0x08,
        .upm_addr_offset = 0x10,
+       .upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
+       .chip_offset = CONFIG_SYS_NAND_CS_DIST,
        .chip_delay = NAND_BIG_DELAY_US,
+       .wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
 };
 
 void board_nand_select_device (struct nand_chip *nand, int chip)