Merge branch 'next' of git://git.denx.de/u-boot

[u-boot] / board / tqc / tqm85xx / sdram.c

diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 503c5e5306d73eb652fb4096ac21ea56a8918ec8..baf073e5489869784f28c6335a1492c32806e52d 100644 (file)
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -65,6 +65,7 @@ sdram_conf_t ddr_cs_conf[] = {
 #define        N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
 
 int cas_latency (void);
+static phys_size_t sdram_setup(int);
 
 /*
  * Autodetect onboard DDR SDRAM on 85xx platforms
@@ -73,7 +74,26 @@ int cas_latency (void);
  *       so this should be extended for other future boards
  *       using this routine!
  */
-long int sdram_setup (int casl)
+phys_size_t fixed_sdram(void)
+{
+       int casl = 0;
+       phys_size_t dram_size = 0;
+
+       casl = cas_latency();
+       dram_size = sdram_setup(casl);
+       if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
+               /*
+                * Try again with default CAS latency
+                */
+               printf("Problem with CAS lantency, using default CL %d/10!\n",
+                      CONFIG_DDR_DEFAULT_CL);
+               dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
+               puts("       ");
+       }
+       return dram_size;
+}
+
+static phys_size_t sdram_setup(int casl)
 {
        int i;
        volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -220,7 +240,7 @@ long int sdram_setup (int casl)
         * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
         *    training
         */
-       ddr->debug_3 |= 0x00000400;
+       ddr->debug[2] |= 0x00000400;
 
        /*
         * 5. Wait 200 micro-seconds
@@ -262,18 +282,18 @@ long int sdram_setup (int casl)
        /*
         * 8. Clear D3[21] to re-enable data training
         */
-       ddr->debug_3 &= ~0x00000400;
+       ddr->debug[2] &= ~0x00000400;
 
        /*
         * 9. Set D2(21) to force data training to run
         */
-       ddr->debug_2 |= 0x00000400;
+       ddr->debug[1] |= 0x00000400;
 
        /*
         * 10. Poll on D2[21] until it is cleared by hardware
         */
        asm ("sync;isync;msync");
-       while (ddr->debug_2 & 0x00000400)
+       while (ddr->debug[1] & 0x00000400)
                asm ("eieio");
 
        /*
@@ -343,6 +363,12 @@ long int sdram_setup (int casl)
        udelay (1000);
 #endif /* CONFIG_TQM8548 */
 
+       /*
+        * get_ram_size() depends on having tlbs for the DDR, but they are
+        * not yet setup because we don't know the size.  Set up a temp
+        * mapping and delete it when done.
+        */
+       setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
        for (i = 0; i < N_DDR_CS_CONF; i++) {
                ddr->cs0_config = ddr_cs_conf[i].reg;
 
@@ -356,6 +382,7 @@ long int sdram_setup (int casl)
                        break;
                }
        }
+       clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
 
 #ifdef CONFIG_TQM8548
        if (i < N_DDR_CS_CONF) {
@@ -374,54 +401,6 @@ long int sdram_setup (int casl)
        return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
 }
 
-phys_size_t initdram (int board_type)
-{
-       long dram_size = 0;
-       int casl;
-
-#if defined(CONFIG_DDR_DLL)
-       /*
-        * This DLL-Override only used on TQM8540 and TQM8560
-        */
-       {
-               volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-               int i, x;
-
-               x = 10;
-
-               /*
-                * Work around to stabilize DDR DLL
-                */
-               gur->ddrdllcr = 0x81000000;
-               asm ("sync; isync; msync");
-               udelay (200);
-               while (gur->ddrdllcr != 0x81000100) {
-                       gur->devdisr = gur->devdisr | 0x00010000;
-                       asm ("sync; isync; msync");
-                       for (i = 0; i < x; i++)
-                               ;
-                       gur->devdisr = gur->devdisr & 0xfff7ffff;
-                       asm ("sync; isync; msync");
-                       x++;
-               }
-       }
-#endif
-
-       casl = cas_latency ();
-       dram_size = sdram_setup (casl);
-       if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
-               /*
-                * Try again with default CAS latency
-                */
-               printf ("Problem with CAS lantency, using default CL %d/10!\n",
-                       CONFIG_DDR_DEFAULT_CL);
-               dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL);
-               puts ("       ");
-       }
-
-       return dram_size;
-}
-
 #if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {