/*
+ * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
+ *
+ * (C) Copyright 2006
+ * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
+ *
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
#include <ioports.h>
#include <flash.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
}
putc ('\n');
-#ifdef CONFIG_PCI
- printf ("PCI1: 32 bit, %d MHz (compiled)\n",
- CONFIG_SYS_CLK_FREQ / 1000000);
-#else
- printf ("PCI1: disabled\n");
-#endif
-
/*
* Initialize local bus.
*/
int misc_init_r (void)
{
- volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
-
/*
* Adjust flash start and offset to detected values
*/
gd->bd->bi_flashoffset = 0;
/*
- * Check if boot FLASH isn't max size
+ * Recalculate CS configuration if second FLASH bank is available
*/
- if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
- memctl->or0 =
- gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
- memctl->br0 =
- gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
-
+ if (flash_info[0].size > 0) {
+ set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
+ (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
+ set_lbc_br(1, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
/*
- * Re-check to get correct base address
+ * Re-check to get correct base address for bank 1
*/
- flash_get_size (gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+ flash_get_size (gd->bd->bi_flashstart, 0);
+ } else {
+ set_lbc_or(1, 0);
+ set_lbc_br(1, 0);
}
/*
- * Check if only one FLASH bank is available
+ * If bank 1 is equipped, bank 0 is mapped after bank 1
+ */
+ set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
+ (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+ set_lbc_br(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
+
+ /*
+ * Re-check to get correct base address for bank 0
*/
- if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
- memctl->or1 = 0;
- memctl->br1 = 0;
+ flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
+
+ /*
+ * Re-do flash protection upon new addresses
+ */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ gd->bd->bi_flashstart, 0xffffffff,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+ /* Monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE, 0xffffffff,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+ /* Environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+ /* Redundant environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_CAN_DRIVER
+/*
+ * Initialize UPMC RAM
+ */
+static void upmc_write (u_char addr, uint val)
+{
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+ out_be32 (&lbc->mdr, val);
+
+ clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
+ MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
+
+ /* dummy access to perform write */
+ out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
+
+ /* normal operation */
+ clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
+}
+#endif /* CONFIG_CAN_DRIVER */
+
+uint get_lbc_clock (void)
+{
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ sys_info_t sys_info;
+ ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
+
+ get_sys_info (&sys_info);
+
+ if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
+#ifdef CONFIG_MPC8548
/*
- * Re-do flash protection upon new addresses
+ * Yes, the entire PQ38 family use the same
+ * bit-representation for twice the clock divider value.
*/
- flash_protect (FLAG_PROTECT_CLEAR,
- gd->bd->bi_flashstart, 0xffffffff,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
- /* Monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
- /* Environment protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
-
- /* Redundant environment protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ clkdiv *= 2;
+#endif
+ return sys_info.freqSystemBus / clkdiv;
}
+ puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
+
return 0;
}
*/
void local_bus_init (void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ uint lbc_mhz = get_lbc_clock () / 1000000;
+
+#ifdef CONFIG_MPC8548
+ uint svr = get_svr ();
+ uint lcrr;
+
+ /*
+ * MPC revision < 2.0
+ * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
+ * Modify engineering use only register at address 0xE_0F20.
+ * "1. Read register at offset 0xE_0F20
+ * 2. And value with 0x0000_FFFF
+ * 3. OR result with 0x0000_0004
+ * 4. Write result back to offset 0xE_0F20."
+ *
+ * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
+ * Modify engineering use only register at address 0xE_0F20.
+ * "1. Read register at offset 0xE_0F20
+ * 2. And value with 0xFFFF_FFDF
+ * 3. Write result back to offset 0xE_0F20."
+ *
+ * Since it is the same register, we do the modification in one step.
+ */
+ if (SVR_MAJ (svr) < 2) {
+ uint dummy = gur->lbiuiplldcr1;
+ dummy &= 0x0000FFDF;
+ dummy |= 0x00000004;
+ gur->lbiuiplldcr1 = dummy;
+ }
- uint clkdiv;
- uint lbc_hz;
- sys_info_t sysinfo;
+ lcrr = CONFIG_SYS_LBC_LCRR;
+
+ /*
+ * Local Bus Clock > 83.3 MHz. According to timing
+ * specifications set LCRR[EADC] to 2 delay cycles.
+ */
+ if (lbc_mhz > 83) {
+ lcrr &= ~LCRR_EADC;
+ lcrr |= LCRR_EADC_2;
+ }
+
+ /*
+ * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
+ * disable PLL bypass for Local Bus Clock > 83 MHz.
+ */
+ if (lbc_mhz >= 66)
+ lcrr &= (~LCRR_DBYP); /* DLL Enabled */
+
+ else
+ lcrr |= LCRR_DBYP; /* DLL Bypass */
+
+ lbc->lcrr = lcrr;
+ asm ("sync;isync;msync");
+
+ /*
+ * According to MPC8548ERMAD Rev.1.3 read back LCRR
+ * and terminate with isync
+ */
+ lcrr = lbc->lcrr;
+ asm ("isync;");
+
+ /* let DLL stabilize */
+ udelay (500);
+
+#else /* !CONFIG_MPC8548 */
/*
* Errata LBC11.
* Fix Local Bus clock glitch when DLL is enabled.
*
- * If localbus freq is < 66Mhz, DLL bypass mode must be used.
- * If localbus freq is > 133Mhz, DLL can be safely enabled.
+ * If localbus freq is < 66MHz, DLL bypass mode must be used.
+ * If localbus freq is > 133MHz, DLL can be safely enabled.
* Between 66 and 133, the DLL is enabled with an override workaround.
*/
- get_sys_info (&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
- lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
-
- if (lbc_hz < 66) {
- lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
- lbc->ltedr = 0xa4c80000; /* DK: !!! */
+ if (lbc_mhz < 66) {
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */
+ lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
+ LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */
- } else if (lbc_hz >= 133) {
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ } else if (lbc_mhz >= 133) {
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
} else {
/*
lbc->lcrr = 0x10000004;
}
- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+ lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */
udelay (200);
/*
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
asm ("sync;isync;msync");
}
+#endif /* !CONFIG_MPC8548 */
+
+#ifdef CONFIG_CAN_DRIVER
+ /*
+ * According to timing specifications EAD must be
+ * set if Local Bus Clock is > 83 MHz.
+ */
+ if (lbc_mhz > 83)
+ set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
+ else
+ set_lbc_or(2, CONFIG_SYS_OR2_CAN);
+ set_lbc_br(2, CONFIG_SYS_BR2_CAN);
+
+ /* LGPL4 is UPWAIT */
+ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
+
+ /* Initialize UPMC for CAN: single read */
+ upmc_write (0x00, 0xFFFFED00);
+ upmc_write (0x01, 0xCCFFCC00);
+ upmc_write (0x02, 0x00FFCF00);
+ upmc_write (0x03, 0x00FFCF00);
+ upmc_write (0x04, 0x00FFDC00);
+ upmc_write (0x05, 0x00FFCF00);
+ upmc_write (0x06, 0x00FFED00);
+ upmc_write (0x07, 0x3FFFCC07);
+
+ /* Initialize UPMC for CAN: single write */
+ upmc_write (0x18, 0xFFFFED00);
+ upmc_write (0x19, 0xCCFFEC00);
+ upmc_write (0x1A, 0x00FFED80);
+ upmc_write (0x1B, 0x00FFED80);
+ upmc_write (0x1C, 0x00FFFC00);
+ upmc_write (0x1D, 0x0FFFEC00);
+ upmc_write (0x1E, 0x0FFFEF00);
+ upmc_write (0x1F, 0x3FFFEC05);
+#endif /* CONFIG_CAN_DRIVER */
}
-#if defined(CONFIG_PCI)
/*
* Initialize PCI Devices, report devices found.
*/
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_mpc85xxads_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
- {}
-};
-#endif
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif /* CONFIG_PCI1 */
-static struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc85xxads_config_table,
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+void pci_init_board (void)
+{
+ struct fsl_pci_info pci_info[2];
+ int first_free_busno = 0;
+ int num = 0;
+ int pcie_ep;
+ __maybe_unused int pcie_configured;
+
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr = in_be32(&gur->devdisr);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ __maybe_unused uint io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+
+#ifdef CONFIG_PCI1
+ uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+ uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
+ uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */
+ uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333333) ? "33" :
+ (pci_speed == 66666666) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pcie_ep ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
+#ifdef CONFIG_PCIX_CHECK
+ if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
+ ushort reg16 =
+ PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
+ PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+ uint dev = PCI_BDF(0, 0, 0);
+
+ /* PCI-X init */
+ if (CONFIG_SYS_CLK_FREQ < 66000000)
+ puts ("PCI-X will only work at 66 MHz\n");
+
+ pci_write_config_word(dev, PCIX_COMMAND, reg16);
+ }
+#endif
+ } else {
+ printf(" PCI1: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
#endif
-};
-#endif /* CONFIG_PCI */
+#ifdef CONFIG_PCIE1
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-void pci_init_board (void)
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf(" PCIE1 connected as %s\n",
+ pcie_ep ? "Endpoint" : "Root Complex");
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
+ } else {
+ printf(" PCIE1: disabled\n");
+ }
+#else
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
+#endif /* CONFIG_PCIE1 */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup (void *blob, bd_t *bd)
{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init (&hose);
-#endif /* CONFIG_PCI */
+ ft_cpu_setup (blob, bd);
+
+ FT_FSL_PCI_SETUP;
}
+#endif /* CONFIG_OF_BOARD_SETUP */
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */
+
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Intialize TSECs first */
+ return pci_eth_init(bis);
+}
projects / u-boot / blobdiff