Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

[u-boot] / board / tqm834x / pci.c

diff --git a/board/tqm834x/pci.c b/board/tqm834x/pci.c
index 6111d034c4a6f77e202b0588760bbcbef273d12f..d896f17aad05f4fe388a22b43c936cffb34457d9 100644 (file)
--- a/board/tqm834x/pci.c
+++ b/board/tqm834x/pci.c
@@ -69,46 +69,46 @@ void
 pci_init_board(void)
 {
        volatile immap_t *      immr;
-       volatile clk8349_t *    clk;
-       volatile law8349_t *    pci_law;
-       volatile pot8349_t *    pci_pot;
-       volatile pcictrl8349_t *        pci_ctrl;
-       volatile pciconf8349_t *        pci_conf;
+       volatile clk83xx_t *    clk;
+       volatile law83xx_t *    pci_law;
+       volatile pot83xx_t *    pci_pot;
+       volatile pcictrl83xx_t *        pci_ctrl;
+       volatile pciconf83xx_t *        pci_conf;
        u16 reg16;
        u32 reg32;
        struct  pci_controller * hose;
 
-       immr = (immap_t *)CFG_IMMRBAR;
-       clk = (clk8349_t *)&immr->clk;
+       immr = (immap_t *)CFG_IMMR;
+       clk = (clk83xx_t *)&immr->clk;
        pci_law = immr->sysconf.pcilaw;
        pci_pot = immr->ios.pot;
        pci_ctrl = immr->pci_ctrl;
        pci_conf = immr->pci_conf;
 
        hose = &pci1_hose;
-       
+
        /*
-        * Configure PCI controller and PCI_CLK_OUTPUT 
+        * Configure PCI controller and PCI_CLK_OUTPUT
         */
 
        /*
         * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
         * line actually used for clocking all external PCI devices in TQM83xx.
-        * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for 
+        * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
         * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
-        * are known to hang the board; this issue is under investigation 
+        * are known to hang the board; this issue is under investigation
         * (13 oct 05)
         */
        reg32 = OCCR_PCICOE1;
-#if 0  
+#if 0
        /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
        reg32 = 0xff000000;
-#endif 
+#endif
        if (clk->spmr & SPMR_CKID) {
                /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR
                 * fields accordingly */
                reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
-               
+
                reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
                          | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
                          | OCCR_PCICD6 | OCCR_PCICD7);
@@ -129,16 +129,16 @@ pci_init_board(void)
         * Configure PCI Local Access Windows
         */
        pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
-       pci_law[0].ar = LAWAR_EN | LAWAR_TRGT_IF_PCI1 | LAWAR_SIZE_512M;
+       pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
 
        pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
-       pci_law[1].ar = LAWAR_EN | LAWAR_TRGT_IF_PCI1 | LAWAR_SIZE_16M;
+       pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
 
        /*
         * Configure PCI Outbound Translation Windows
         */
 
-       /* PCI1 mem space */ 
+       /* PCI1 mem space */
        pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
        pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
        pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
@@ -152,12 +152,12 @@ pci_init_board(void)
         * Configure PCI Inbound Translation Windows
         */
 
-       /* we need RAM mapped to PCI space for the devices to 
-        * access main memory */ 
+       /* we need RAM mapped to PCI space for the devices to
+        * access main memory */
        pci_ctrl[0].pitar1 = 0x0;
        pci_ctrl[0].pibar1 = 0x0;
        pci_ctrl[0].piebar1 = 0x0;
-       pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_IWS_256M;
+       pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M;
 
        hose->first_busno = 0;
        hose->last_busno = 0xff;
@@ -179,15 +179,15 @@ pci_init_board(void)
        /* System memory space */
        pci_set_region(hose->regions + 2,
                       CONFIG_PCI_SYS_MEM_BUS,
-                       CONFIG_PCI_SYS_MEM_PHYS,
-                       CONFIG_PCI_SYS_MEM_SIZE,
-                       PCI_REGION_MEM | PCI_REGION_MEMORY);
-                      
+                      CONFIG_PCI_SYS_MEM_PHYS,
+                      CONFIG_PCI_SYS_MEM_SIZE,
+                      PCI_REGION_MEM | PCI_REGION_MEMORY);
+
        hose->region_count = 3;
 
        pci_setup_indirect(hose,
-                          (CFG_IMMRBAR+0x8300),
-                          (CFG_IMMRBAR+0x8304));
+                          (CFG_IMMR+0x8300),
+                          (CFG_IMMR+0x8304));
 
        pci_register_hose(hose);
 
@@ -195,18 +195,18 @@ pci_init_board(void)
         * Write to Command register
         */
        reg16 = 0xff;
-       pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, 
+       pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
                                        &reg16);
        reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-       pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, 
+       pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
                                        reg16);
 
        /*
         * Clear non-reserved bits in status register.
         */
-       pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, 
+       pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
                                        0xffff);
-       pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 
+       pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
                                        0x80);
 
 #ifdef CONFIG_PCI_SCAN_SHOW