Merge branch 'master' of /home/wd/git/u-boot/master/

[u-boot] / board / tqm834x / tqm834x.c

diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index 9e620eb27ce32c41bb68ee73101c5b03eb626697..aea985ccc6c1a85476276ed34d2169e8fd7849bb 100644 (file)
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -27,13 +27,11 @@
 #include <mpc83xx.h>
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
 #include <asm-ppc/mmu.h>
-
-#if defined(CONFIG_PCI)
 #include <pci.h>
-#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define IOSYNC                 asm("eieio")
 #define ISYNC                  asm("isync")
@@ -60,7 +58,6 @@ int tqm834x_num_flash_banks;
 /* External definitions */
 ulong flash_get_size (ulong base, int banknum);
 extern flash_info_t flash_info[];
-extern long spd_sdram (void);
 
 /* Local functions */
 static int detect_num_flash_banks(void);
@@ -70,7 +67,7 @@ static void set_cs_config(short cs, long config);
 static void set_ddr_config(void);
 
 /* Local variable */
-static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+static volatile immap_t *im = (immap_t *)CFG_IMMR;
 
 /**************************************************************************
  * Board initialzation after relocation to RAM. Used to detect the number
@@ -80,7 +77,7 @@ int board_early_init_r (void) {
        /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
                return 0;
-       
+
        /* detect the number of Flash banks */
        return detect_num_flash_banks();
 }
@@ -111,11 +108,11 @@ long int initdram (int board_type)
        set_ddr_config();
 
        udelay(200);
-       
+
        /* enable DDR controller */
        im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
                SDRAM_CFG_SREN |
-               SDRAM_CFG_SDRAM_TYPE_DDR);
+               SDRAM_CFG_SDRAM_TYPE_DDR1);
        SYNC;
 
        /* size detection */
@@ -145,37 +142,31 @@ int checkboard (void)
        puts("Board: TQM834x\n");
 
 #ifdef CONFIG_PCI
-       printf("PCI1:  32 bit, %d MHz (compiled)\n",
-                       CONFIG_SYS_CLK_FREQ / 1000000);
-#else
-       printf("PCI1:  disabled\n");
-#endif
-
-       return 0;
-}
+       volatile immap_t * immr;
+       u32 w, f;
 
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found
- */
-
-/* FIXME: No PCI support */
+       immr = (immap_t *)CFG_IMMR;
+       if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
+               printf("PCI:   NOT in host mode..?!\n");
+               return 0;
+       }
 
-#endif /* CONFIG_PCI */
+       /* get bus width */
+       w = 32;
+       if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
+               w = 64;
 
-/**************************************************************************
- * pci_init_board()
- */
-void
-pci_init_board(void)
-{
-#ifdef CONFIG_PCI
-       extern void pci_mpc83xx_init(volatile struct pci_controller *hose);
+       /* get clock */
+       f = gd->pci_clk;
 
-       pci_mpc83xx_init(hose);
-#endif /* CONFIG_PCI */
+       printf("PCI1:  %d bit, %d MHz\n", w, f / 1000000);
+#else
+       printf("PCI:   disabled\n");
+#endif
+       return 0;
 }
 
+
 /**************************************************************************
  *
  * Local functions
@@ -200,7 +191,7 @@ static int detect_num_flash_banks(void)
        ulong total_size;
 
        tqm834x_num_flash_banks = 2;    /* assume two banks */
-       
+
        /* Get bank 1 and 2 information */
        bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
        debug("Bank1 size: %lu\n", bank1_size);
@@ -326,10 +317,10 @@ static long int get_ddr_bank_size(short cs, volatile long *base)
                set_cs_config(cs, 0);
                return 0;
        }
-               
+
        debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
                        conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
-       
+
        /* configure cs ro detected params */
        set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
                        conf[detected].col);
@@ -375,7 +366,7 @@ static void set_ddr_config(void) {
        im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
                DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
        SYNC;
-       
+
        /* timing configuration */
        im->ddr.timing_cfg_1 =
                (4 << TIMING_CFG1_PRETOACT_SHIFT) |
@@ -395,9 +386,9 @@ static void set_ddr_config(void) {
        /* don't enable DDR controller yet */
        im->ddr.sdram_cfg =
                SDRAM_CFG_SREN |
-               SDRAM_CFG_SDRAM_TYPE_DDR;
+               SDRAM_CFG_SDRAM_TYPE_DDR1;
        SYNC;
-       
+
        /* Set SDRAM mode */
        im->ddr.sdram_mode =
                ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
@@ -413,4 +404,30 @@ static void set_ddr_config(void) {
                (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
                (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
        SYNC;
+
+       /* Workaround for DDR6 Erratum
+        * see MPC8349E Device Errata Rev.8, 2/2006
+        * This workaround influences the MPC internal "input enables"
+        * dependent on CAS latency and MPC revision. According to errata
+        * sheet the internal reserved registers for this workaround are
+        * not available from revision 2.0 and up.
+        */
+
+       /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
+        * (0x200)
+        */
+       if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
+
+               /* There is a internal reserved register at IMMRBAR+0x2F00
+                * which has to be written with a certain value defined by
+                * errata sheet.
+                */
+               u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
+
+#if defined(DDR_CASLAT_20)
+               *reserved_p = 0x201c0000;
+#else
+               *reserved_p = 0x202c0000;
+#endif
+       }
 }