#include <common.h>
#include <asm/arch/pxa-regs.h>
#include <netdev.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
-#if CONFIG_POLARIS
+#if CONFIG_MK_POLARIS
#define BOOT_CONSOLE "serial_stuart"
#else
#define BOOT_CONSOLE "serial_ffuart"
int usb_board_init(void)
{
- UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
- ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
+ writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
+ ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
+ UHCHR);
- UHCHR |= UHCHR_FSBIR;
+ writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
- while (UHCHR & UHCHR_FSBIR);
+ while (readl(UHCHR) & UHCHR_FSBIR)
+ ;
- UHCHR &= ~UHCHR_SSE;
- UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
+ writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
+ writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
/* Clear any OTG Pin Hold */
- if (PSSR & PSSR_OTGPH)
- PSSR |= PSSR_OTGPH;
+ if (readl(PSSR) & PSSR_OTGPH)
+ writel(readl(PSSR) | PSSR_OTGPH, PSSR);
- UHCRHDA &= ~(RH_A_NPS);
- UHCRHDA |= RH_A_PSM;
+ writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
+ writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
/* Set port power control mask bits, only 3 ports. */
- UHCRHDB |= (0x7<<17);
+ writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
return 0;
}
void usb_board_stop(void)
{
- UHCHR |= UHCHR_FHR;
+ writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
udelay(11);
- UHCHR &= ~UHCHR_FHR;
+ writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
- UHCCOMS |= 1;
+ writel(readl(UHCCOMS) | 1, UHCCOMS);
udelay(10);
- CKEN &= ~CKEN10_USBHOST;
+ writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
return;
}
int board_init (void)
{
- /* memory and cpu-speed are setup before relocation */
- /* so we do _nothing_ here */
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
/* arch number of ConXS Board */
gd->bd->bi_arch_number = 776;
return &serial_ffuart_device;
}
-int dram_init (void)
+extern void pxa_dram_init(void);
+int dram_init(void)
+{
+ pxa_dram_init();
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
- gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
- gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
- gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
- gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
-
- return 0;
}
#ifdef CONFIG_DRIVER_DM9000