Merge branch 'mimc200'

[u-boot] / board / v38b / v38b.c

diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
index ace4aa2caed9f437df82d1571827de84b4465304..9e7c1d7e55bf96e4f4086d1a21ee183cb13ce2a9 100644 (file)
--- a/board/v38b/v38b.c
+++ b/board/v38b/v38b.c
@@ -29,7 +29,7 @@
 #include <asm/processor.h>
 
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start(int hi_addr)
 {
        long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -68,16 +68,16 @@ static void sdram_start(int hi_addr)
        *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
        __asm__ volatile ("sync");
 }
-#endif /* !CFG_RAMBOOT */
+#endif /* !CONFIG_SYS_RAMBOOT */
 
 
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
        uint svr, pvr;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
        ulong test1, test2;
 
        /* setup SDRAM chip selects */
@@ -98,9 +98,9 @@ long int initdram(int board_type)
 
        /* find RAM size using SDRAM CS0 only */
        sdram_start(0);
-       test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
        sdram_start(1);
-       test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+       test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
        if (test1 > test2) {
                sdram_start(0);
                dramsize = test1;
@@ -123,10 +123,10 @@ long int initdram(int board_type)
        /* find RAM size using SDRAM CS1 only */
        if (!dramsize)
                sdram_start(0);
-       test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+       test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
        if (!dramsize) {
                sdram_start(1);
-               test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+               test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
        }
        if (test1 > test2) {
                sdram_start(0);
@@ -145,7 +145,7 @@ long int initdram(int board_type)
        else
                *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
        /* retrieve size of memory connected to SDRAM CS0 */
        dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -161,7 +161,7 @@ long int initdram(int board_type)
        else
                dramsize2 = 0;
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
        /*
         * On MPC5200B we need to set the special configuration delay in the
@@ -223,8 +223,20 @@ int board_early_init_r(void)
        return 0;
 }
 
+extern void board_get_enetaddr(uchar *enetaddr);
+int misc_init_r(void)
+{
+       uchar enetaddr[6];
+
+       if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+               board_get_enetaddr(enetaddr);
+               eth_putenv_enetaddr("ethaddr", enetaddr);
+       }
+
+       return 0;
+}
 
-#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 void init_ide_reset(void)
 {
        debug("init_ide_reset\n");
@@ -248,7 +260,7 @@ void ide_set_reset(int idereset)
        } else
                *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 }
-#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+#endif
 
 
 #ifdef CONFIG_HW_WATCHDOG