Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[u-boot] / board / xilinx / zynq / board.c

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index a5b9bdef46a0b97da7bbad6fb920f4ade18a54c7..738c31c6ee1f568cc95a6dd47ce34579f2853b64 100644 (file)
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -5,6 +5,9 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
+#include <fpga.h>
+#include <mmc.h>
 #include <netdev.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
@@ -12,26 +15,24 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* Bootmode setting values */
-#define ZYNQ_BM_MASK           0x0F
-#define ZYNQ_BM_NOR            0x02
-#define ZYNQ_BM_SD             0x05
-#define ZYNQ_BM_JTAG           0x0
-
-#ifdef CONFIG_FPGA
-Xilinx_desc fpga;
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static xilinx_desc fpga;
 
 /* It can be done differently */
-Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
-Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
+static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
+static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif
 
 int board_init(void)
 {
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
        u32 idcode;
 
        idcode = zynq_slcr_get_idcode();
@@ -40,12 +41,18 @@ int board_init(void)
        case XILINX_ZYNQ_7010:
                fpga = fpga010;
                break;
+       case XILINX_ZYNQ_7015:
+               fpga = fpga015;
+               break;
        case XILINX_ZYNQ_7020:
                fpga = fpga020;
                break;
        case XILINX_ZYNQ_7030:
                fpga = fpga030;
                break;
+       case XILINX_ZYNQ_7035:
+               fpga = fpga035;
+               break;
        case XILINX_ZYNQ_7045:
                fpga = fpga045;
                break;
@@ -55,9 +62,8 @@ int board_init(void)
        }
 #endif
 
-       icache_enable();
-
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
        fpga_init();
        fpga_add(fpga_xilinx, &fpga);
 #endif
@@ -85,7 +91,14 @@ int board_late_init(void)
        return 0;
 }
 
-#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+       puts("Board:\tXilinx Zynq\n");
+       return 0;
+}
+#endif
+
 int board_eth_init(bd_t *bis)
 {
        u32 ret = 0;
@@ -110,16 +123,17 @@ int board_eth_init(bd_t *bis)
 #if defined(CONFIG_ZYNQ_GEM)
 # if defined(CONFIG_ZYNQ_GEM0)
        ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
-                                               CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
+                                  CONFIG_ZYNQ_GEM_PHY_ADDR0,
+                                  CONFIG_ZYNQ_GEM_EMIO0);
 # endif
 # if defined(CONFIG_ZYNQ_GEM1)
        ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
-                                               CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
+                                  CONFIG_ZYNQ_GEM_PHY_ADDR1,
+                                  CONFIG_ZYNQ_GEM_EMIO1);
 # endif
 #endif
        return ret;
 }
-#endif
 
 #ifdef CONFIG_CMD_MMC
 int board_mmc_init(bd_t *bd)
@@ -140,8 +154,27 @@ int board_mmc_init(bd_t *bd)
 
 int dram_init(void)
 {
+#ifdef CONFIG_OF_CONTROL
+       int node;
+       fdt_addr_t addr;
+       fdt_size_t size;
+       const void *blob = gd->fdt_blob;
+
+       node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
+                                            "memory", 7);
+       if (node == -FDT_ERR_NOTFOUND) {
+               debug("ZYNQ DRAM: Can't get memory node\n");
+               return -1;
+       }
+       addr = fdtdec_get_addr_size(blob, node, "reg", &size);
+       if (addr == FDT_ADDR_T_NONE || size == 0) {
+               debug("ZYNQ DRAM: Can't get base address or size\n");
+               return -1;
+       }
+       gd->ram_size = size;
+#else
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
+#endif
        zynq_ddrc_init();
 
        return 0;