arm64: zynqmp: Setup MMU map for DDR at run time

[u-boot] / board / xilinx / zynqmp / zynqmp.c

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 0d1bd5412b166e37f04f7cf67197e668def35edb..911cd52e0c40c51f8820bccff1ffcdc1b70755e3 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2014 - 2015 Xilinx, Inc.
  * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -10,11 +9,13 @@
 #include <ahci.h>
 #include <scsi.h>
 #include <malloc.h>
+#include <wdt.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/psu_init_gpl.h>
 #include <asm/io.h>
+#include <dm/uclass.h>
 #include <usb.h>
 #include <dwc3-uboot.h>
 #include <zynqmppl.h>
@@ -23,6 +24,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
+static struct udevice *watchdog_dev;
+#endif
+
 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
     !defined(CONFIG_SPL_BUILD)
 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
@@ -282,6 +287,11 @@ int board_early_init_f(void)
        ret = psu_init();
 #endif
 
+#if defined(CONFIG_WDT) && !defined(CONFIG_SPL_BUILD)
+       /* bss is not cleared at time when watchdog_reset() is called */
+       watchdog_dev = NULL;
+#endif
+
        return ret;
 }
 
@@ -300,9 +310,40 @@ int board_init(void)
        }
 #endif
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
+       if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
+               puts("Watchdog: Not found!\n");
+       } else {
+               wdt_start(watchdog_dev, 0, 0);
+               puts("Watchdog: Started\n");
+       }
+#endif
+
        return 0;
 }
 
+#ifdef CONFIG_WATCHDOG
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+# if !defined(CONFIG_SPL_BUILD)
+       static ulong next_reset;
+       ulong now;
+
+       if (!watchdog_dev)
+               return;
+
+       now = timer_get_us();
+
+       /* Do not reset the watchdog too often */
+       if (now > next_reset) {
+               wdt_reset(watchdog_dev);
+               next_reset = now + 1000;
+       }
+# endif
+}
+#endif
+
 int board_early_init_r(void)
 {
        u32 val;
@@ -364,7 +405,15 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 int dram_init_banksize(void)
 {
-       return fdtdec_setup_memory_banksize();
+       int ret;
+
+       ret = fdtdec_setup_memory_banksize();
+       if (ret)
+               return ret;
+
+       mem_map_fill();
+
+       return 0;
 }
 
 int dram_init(void)
@@ -375,9 +424,22 @@ int dram_init(void)
        return 0;
 }
 #else
+int dram_init_banksize(void)
+{
+#if defined(CONFIG_NR_DRAM_BANKS)
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_dram[0].size = get_effective_memsize();
+#endif
+
+       mem_map_fill();
+
+       return 0;
+}
+
 int dram_init(void)
 {
-       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+       gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+                                   CONFIG_SYS_SDRAM_SIZE);
 
        return 0;
 }