]> git.sur5r.net Git - u-boot/blobdiff - board/zylonite/nand.c
Add support for operating system OSE
[u-boot] / board / zylonite / nand.c
index 895fb2bacdf8e5e20d8ca4712d54c08f5b5181a9..7cad1ac049cbdc7c955cb88b5c3cfae84724d3f8 100644 (file)
@@ -23,7 +23,6 @@
 #include <common.h>
 
 #if defined(CONFIG_CMD_NAND)
-#ifdef CONFIG_NEW_NAND_CODE
 
 #include <nand.h>
 #include <asm/arch/pxa-regs.h>
@@ -46,8 +45,6 @@
 # define DFC_DEBUG3(fmt, args...)
 #endif
 
-#define MIN(x, y)              ((x < y) ? x : y)
-
 /* These really don't belong here, as they are specific to the NAND Model */
 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 
@@ -201,7 +198,7 @@ static unsigned long get_delta(unsigned long start)
 static void wait_us(unsigned long us)
 {
        unsigned long start = OSCR;
-       us *= OSCR_CLK_FREQ;
+       us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
 
        while (get_delta(start) < us) {
                /* do nothing */
@@ -222,9 +219,11 @@ static unsigned long dfc_wait_event(unsigned long event)
        if(!event)
                return 0xff000000;
        else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
-               timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+               timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
+                                       * OSCR_CLK_FREQ, 1000);
        else
-               timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
+               timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
+                                       * OSCR_CLK_FREQ, 1000);
 
        while(1) {
                ndsr = NDSR;
@@ -556,7 +555,4 @@ int board_nand_init(struct nand_chip *nand)
        return 0;
 }
 
-#else
- #error "U-Boot legacy NAND support not available for Monahans DFC."
-#endif
 #endif