#include <asm/processor.h>
#elif defined (CONFIG_5xx)
#include <mpc5xx.h>
+#elif defined (CONFIG_MPC5200)
+#include <mpc5xxx.h>
+#elif defined (CONFIG_MPC86xx)
+extern void mpc86xx_reginfo(void);
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_REGINFO)
int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
* May be some CPM info here?
*/
-/* DBU[dave@cray.com] For the CRAY-L1, but should be generically 405gp */
#elif defined (CONFIG_405GP)
printf ("\n405GP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd));
puts ("\n\n");
-/* For the BUBINGA (IBM 405EP eval) but should be generically 405ep */
+
#elif defined(CONFIG_405EP)
printf ("\n405EP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n"
puts ("\nU-Bus to IMB3 Bus Interface\n");
printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
puts ("\n\n");
-#endif /* CONFIG_5xx */
- return 0;
-}
-#endif /* CONFIG_COMMANDS & CFG_CMD_REGINFO */
+#elif defined(CONFIG_MPC5200)
+ puts ("\nMPC5200 registers\n");
+ printf ("MBAR=%08x\n", CFG_MBAR);
+ puts ("Memory map registers\n");
+ printf ("\tCS0: start %08X\tstop %08X\tconfig %08X\ten %d\n",
+ *(volatile ulong*)MPC5XXX_CS0_START,
+ *(volatile ulong*)MPC5XXX_CS0_STOP,
+ *(volatile ulong*)MPC5XXX_CS0_CFG,
+ (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
+ printf ("\tCS1: start %08X\tstop %08X\tconfig %08X\ten %d\n",
+ *(volatile ulong*)MPC5XXX_CS1_START,
+ *(volatile ulong*)MPC5XXX_CS1_STOP,
+ *(volatile ulong*)MPC5XXX_CS1_CFG,
+ (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
+ printf ("\tCS2: start %08X\tstop %08X\tconfig %08X\ten %d\n",
+ *(volatile ulong*)MPC5XXX_CS2_START,
+ *(volatile ulong*)MPC5XXX_CS2_STOP,
+ *(volatile ulong*)MPC5XXX_CS2_CFG,
+ (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
+ printf ("\tCS3: start %08X\tstop %08X\tconfig %08X\ten %d\n",
+ *(volatile ulong*)MPC5XXX_CS3_START,
+ *(volatile ulong*)MPC5XXX_CS3_STOP,
+ *(volatile ulong*)MPC5XXX_CS3_CFG,
+ (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
+ printf ("\tCS4: start %08X\tstop %08X\tconfig %08X\ten %d\n",
+ *(volatile ulong*)MPC5XXX_CS4_START,
+ *(volatile ulong*)MPC5XXX_CS4_STOP,
+ *(volatile ulong*)MPC5XXX_CS4_CFG,
+ (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
+ printf ("\tCS5: start %08X\tstop %08X\tconfig %08X\ten %d\n",
+ *(volatile ulong*)MPC5XXX_CS5_START,
+ *(volatile ulong*)MPC5XXX_CS5_STOP,
+ *(volatile ulong*)MPC5XXX_CS5_CFG,
+ (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
+ printf ("\tCS6: start %08X\tstop %08X\tconfig %08X\ten %d\n",
+ *(volatile ulong*)MPC5XXX_CS6_START,
+ *(volatile ulong*)MPC5XXX_CS6_STOP,
+ *(volatile ulong*)MPC5XXX_CS6_CFG,
+ (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
+ printf ("\tCS7: start %08X\tstop %08X\tconfig %08X\ten %d\n",
+ *(volatile ulong*)MPC5XXX_CS7_START,
+ *(volatile ulong*)MPC5XXX_CS7_STOP,
+ *(volatile ulong*)MPC5XXX_CS7_CFG,
+ (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
+ printf ("\tBOOTCS: start %08X\tstop %08X\tconfig %08X\ten %d\n",
+ *(volatile ulong*)MPC5XXX_BOOTCS_START,
+ *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
+ *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
+ (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
+ printf ("\tSDRAMCS0: %08X\n",
+ *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
+ printf ("\tSDRAMCS1: %08X\n",
+ *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
+#elif defined(CONFIG_MPC86xx)
+ mpc86xx_reginfo();
+
+#elif defined(CONFIG_BLACKFIN)
+ puts("\nSystem Configuration registers\n");
+
+ puts("\nPLL Registers\n");
+ printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
+ bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
+ printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
+ bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
+ printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
+
+ puts("\nEBIU AMC Registers\n");
+ printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
+ printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
+ bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
+# ifdef EBIU_MODE
+ printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
+ bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
+ printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
+ bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
+# endif
+
+# ifdef EBIU_RSTCTL
+ puts("\nEBIU DDR Registers\n");
+ printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
+ bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
+ printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
+ bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
+ printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
+ bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
+ printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
+ bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
+# else
+ puts("\nEBIU SDC Registers\n");
+ printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
+ bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
+ printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
+ bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
+# endif
+
+#endif /* CONFIG_BLACKFIN */
+ return 0;
+}
/**************************************************/
-#if (defined(CONFIG_8xx) || defined(CONFIG_405GP) || defined(CONFIG_405EP)) && \
- (CONFIG_COMMANDS & CFG_CMD_REGINFO)
-
+#if defined(CONFIG_CMD_REGINFO)
U_BOOT_CMD(
reginfo, 2, 1, do_reginfo,
"reginfo - print register information\n",
projects / u-boot / blobdiff