fpga: zynqmp: Add secure bitstream loading for ZynqMP

[u-boot] / common / image.c

diff --git a/common/image.c b/common/image.c
index 14be3caf97303ce8de9e3ee0701d798a0695e08a..214ac3372062b94ca78e8828c3ee9ad8f2301419 100644 (file)
--- a/common/image.c
+++ b/common/image.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2008 Semihalf
  *
  * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef USE_HOSTCC
@@ -86,6 +85,7 @@ static const table_entry_t uimage_arch[] = {
        {       IH_ARCH_ARC,            "arc",          "ARC",          },
        {       IH_ARCH_X86_64,         "x86_64",       "AMD x86_64",   },
        {       IH_ARCH_XTENSA,         "xtensa",       "Xtensa",       },
+       {       IH_ARCH_RISCV,          "riscv",        "RISC-V",       },
        {       -1,                     "",             "",             },
 };
 
@@ -100,6 +100,7 @@ static const table_entry_t uimage_os[] = {
        {       IH_OS_OSE,      "ose",          "Enea OSE",             },
        {       IH_OS_PLAN9,    "plan9",        "Plan 9",               },
        {       IH_OS_RTEMS,    "rtems",        "RTEMS",                },
+       {       IH_OS_TEE,      "tee",          "Trusted Execution Environment" },
        {       IH_OS_U_BOOT,   "u-boot",       "U-Boot",               },
        {       IH_OS_VXWORKS,  "vxworks",      "VxWorks",              },
 #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC)
@@ -144,7 +145,8 @@ static const table_entry_t uimage_type[] = {
        {       IH_TYPE_PBLIMAGE,   "pblimage",   "Freescale PBL Boot Image",},
        {       IH_TYPE_RAMDISK,    "ramdisk",    "RAMDisk Image",      },
        {       IH_TYPE_SCRIPT,     "script",     "Script",             },
-       {       IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",},
+       {       IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SoCFPGA CV/AV preloader",},
+       {       IH_TYPE_SOCFPGAIMAGE_V1, "socfpgaimage_v1", "Altera SoCFPGA A10 preloader",},
        {       IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
        {       IH_TYPE_UBLIMAGE,   "ublimage",   "Davinci UBL image",},
        {       IH_TYPE_MXSIMAGE,   "mxsimage",   "Freescale MXS Boot Image",},
@@ -157,10 +159,12 @@ static const table_entry_t uimage_type[] = {
        {       IH_TYPE_VYBRIDIMAGE, "vybridimage",  "Vybrid Boot Image", },
        {       IH_TYPE_ZYNQIMAGE,  "zynqimage",  "Xilinx Zynq Boot Image" },
        {       IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" },
+       {       IH_TYPE_ZYNQMPBIF,  "zynqmpbif",  "Xilinx ZynqMP Boot Image (bif)" },
        {       IH_TYPE_FPGA,       "fpga",       "FPGA Image" },
        {       IH_TYPE_TEE,        "tee",        "Trusted Execution Environment Image",},
        {       IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT" },
        {       IH_TYPE_PMMC,        "pmmc",        "TI Power Management Micro-Controller Firmware",},
+       {       IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" },
        {       -1,                 "",           "",                   },
 };