[MIPS] Initialize CP0 Cause before setting up CP0 Status register

[u-boot] / common / miiphybb.c

diff --git a/common/miiphybb.c b/common/miiphybb.c
index b6af88f7d6866ecf417ebd5c24161f0bfeee8e96..537c15d29b85e8bb226c050a3bbab10c70692ce0 100644 (file)
--- a/common/miiphybb.c
+++ b/common/miiphybb.c
@@ -41,7 +41,7 @@
 static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
 {
        int j;                  /* counter */
-#ifndef CONFIG_EP8248
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
        volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
 #endif
 
@@ -121,11 +121,12 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
  * Returns:
  *   0 on success
  */
-int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+int bb_miiphy_read (char *devname, unsigned char addr,
+               unsigned char reg, unsigned short *value)
 {
        short rdreg;            /* register working value */
        int j;                  /* counter */
-#ifndef CONFIG_EP8248
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
        volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
 #endif
 
@@ -188,10 +189,11 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
  * Returns:
  *   0 on success
  */
-int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+int bb_miiphy_write (char *devname, unsigned char addr,
+               unsigned char reg, unsigned short value)
 {
        int j;                  /* counter */
-#ifndef CONFIG_EP8248
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
        volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, MDIO_PORT);
 #endif