mpc512x: Use serial_setbrg() in serial_init() to not duplicate the code

[u-boot] / cpu / 74xx_7xx / kgdb.S

diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S
index c3132c29bcf20157e6661307740544378f9ce73d..ad487cdaf45007b03944d2136774a70b989ab03d 100644 (file)
--- a/cpu/74xx_7xx/kgdb.S
+++ b/cpu/74xx_7xx/kgdb.S
@@ -20,8 +20,6 @@
  * MA 02111-1307USA
  */
 
-/* note - this won't work with the 74xx cpus.  needs more work [josh] */
-
 #include <config.h>
 #include <command.h>
 #include <74xx_7xx.h>
@@ -33,7 +31,7 @@
 #include <asm/cache.h>
 #include <asm/mmu.h>
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 
  /*
  * cache flushing routines for kgdb
@@ -41,33 +39,39 @@
 
        .globl  kgdb_flush_cache_all
 kgdb_flush_cache_all:
-       lis     r3, IDC_INVALL@h
-       mtspr   DC_CST, r3
-       sync
-       lis     r3, IDC_INVALL@h
-       mtspr   IC_CST, r3
+       lis     r3,0
+       addis   r4,r0,0x0040
+kgdb_flush_loop:
+       lwz     r5,0(r3)
+       addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
+       cmp     0,0,r3,r4
+       bne     kgdb_flush_loop
        SYNC
+       mfspr   r3,1008
+       ori     r3,r3,0x8800
+       mtspr   1008,r3
+       sync
        blr
 
        .globl  kgdb_flush_cache_range
 kgdb_flush_cache_range:
-       li      r5,CFG_CACHELINE_SIZE-1
+       li      r5,CONFIG_SYS_CACHELINE_SIZE-1
        andc    r3,r3,r5
        subf    r4,r3,r4
        add     r4,r4,r5
-       srwi.   r4,r4,CFG_CACHELINE_SHIFT
+       srwi.   r4,r4,CONFIG_SYS_CACHELINE_SHIFT
        beqlr
        mtctr   r4
        mr      r6,r3
 1:     dcbst   0,r3
-       addi    r3,r3,CFG_CACHELINE_SIZE
+       addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
        bdnz    1b
        sync                            /* wait for dcbst's to get to ram */
        mtctr   r4
 2:     icbi    0,r6
-       addi    r6,r6,CFG_CACHELINE_SIZE
+       addi    r6,r6,CONFIG_SYS_CACHELINE_SIZE
        bdnz    2b
        SYNC
        blr
 
-#endif /* CFG_CMD_KGDB */
+#endif