/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
/* Set-up PLL */
mov r3, #0xAA
mov r4, #0x55
- /* First disconnect and disable the PLL */
+ /* First disconnect and disable the PLL */
ldr r0, PLLCON_ADR
mov r1, #0x00
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
- str r4, [r0] /* feed sequence done */
+ str r4, [r0] /* feed sequence done */
/* Set new M and P values */
ldr r0, PLLCFG_ADR
mov r1, #0x23 /* M=4 and P=2 */
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
str r4, [r0] /* feed sequence done */
- /* Wait for the lock */
+ /* Wait for the lock */
ldr r0, PLLSTAT_ADR
mov r1, #0x400 /* lock bit */
-lock_loop:
+lock_loop:
ldr r2, [r0]
and r2, r1, r2
cmp r2, #0
str r1, [r0]
ldr r0, PLLFEED_ADR /* start feed sequence */
str r3, [r0]
- str r4, [r0] /* feed sequence done */
+ str r4, [r0] /* feed sequence done */
/* Set-up VPBDIV register */
ldr r0, VPBDIV_ADR
mov r1, #0x01 /* VPB clock is same as process clock */
add r8, sp, #S_PC
ldr r2, _armboot_start
- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr