Merge branch 'fixes' into cleanups

[u-boot] / cpu / arm926ejs / cpu.c

diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 748a21a416e395a537badbbdf549168f43535f81..48a2c0bf213d9bb33d73438a85e7f1bd7faa3d40 100644 (file)
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <arm926ejs.h>
 
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /* read co-processor 15, register #1 (control register) */
 static unsigned long read_p15_c1 (void)
 {
@@ -69,21 +73,21 @@ static void cp_delay (void)
 {
        volatile int i;
 
-       /* Many OMAP regs need at least 2 nops  */
+       /* copro seems to need some delay between reading and writing */
        for (i = 0; i < 100; i++);
 }
 
-/* See also ARM Ref. Man. */
+/* See also ARM926EJ-S Technical Reference Manual */
 #define C1_MMU         (1<<0)          /* mmu off/on */
 #define C1_ALIGN       (1<<1)          /* alignment faults off/on */
 #define C1_DC          (1<<2)          /* dcache off/on */
-#define C1_WB          (1<<3)          /* merging write buffer on/off */
-#define C1_BIG_ENDIAN  (1<<7)  /* big endian off/on */
+
+#define C1_BIG_ENDIAN  (1<<7)          /* big endian off/on */
 #define C1_SYS_PROT    (1<<8)          /* system protection */
 #define C1_ROM_PROT    (1<<9)          /* ROM protection */
 #define C1_IC          (1<<12)         /* icache off/on */
-#define C1_HIGH_VECTORS        (1<<13) /* location of vectors: low/high addresses */
-#define RESERVED_1     (0xf << 3)      /* must be 111b for R/W */
+#define C1_HIGH_VECTORS        (1<<13)         /* location of vectors: low/high addresses */
+
 
 int cpu_init (void)
 {
@@ -91,9 +95,7 @@ int cpu_init (void)
         * setup up stacks if necessary
         */
 #ifdef CONFIG_USE_IRQ
-       DECLARE_GLOBAL_DATA_PTR;
-
-       IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_LEN - 4;
+       IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
        FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 #endif
        return 0;
@@ -120,38 +122,64 @@ int cleanup_before_linux (void)
        /* flush I/D-cache */
        i = 0;
        asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+
        return (0);
 }
 
 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-       extern void reset_cpu (ulong addr);
-
        disable_interrupts ();
        reset_cpu (0);
        /*NOTREACHED*/
        return (0);
 }
 
-void icache_enable (void)
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_enable(uint32_t cache_bit)
 {
-       ulong reg;
+       uint32_t reg;
 
-       reg = read_p15_c1 ();           /* get control reg. */
-       cp_delay ();
-       write_p15_c1 (reg | C1_IC);
+       reg = read_p15_c1();    /* get control reg. */
+       cp_delay();
+       write_p15_c1(reg | cache_bit);
 }
 
-void icache_disable (void)
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_disable(uint32_t cache_bit)
 {
-       ulong reg;
+       uint32_t reg;
+
+       reg = read_p15_c1();
+       cp_delay();
+       write_p15_c1(reg & ~cache_bit);
+}
 
-       reg = read_p15_c1 ();
-       cp_delay ();
-       write_p15_c1 (reg & ~C1_IC);
+void icache_enable(void)
+{
+       cache_enable(C1_IC);
+}
+
+void icache_disable(void)
+{
+       cache_disable(C1_IC);
+}
+
+int icache_status(void)
+{
+       return (read_p15_c1() & C1_IC) != 0;
+}
+
+void dcache_enable(void)
+{
+       cache_enable(C1_DC);
+}
+
+void dcache_disable(void)
+{
+       cache_disable(C1_DC);
 }
 
-int icache_status (void)
+int dcache_status(void)
 {
-       return (read_p15_c1 () & C1_IC) != 0;
+       return (read_p15_c1() & C1_DC) != 0;
 }