Fix e-mail address of Gary Jennejohn.

[u-boot] / cpu / arm926ejs / cpu.c

diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 48a2c0bf213d9bb33d73438a85e7f1bd7faa3d40..518c5e0b3fbcb6ec5044c163499854d608e396da 100644 (file)
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -4,7 +4,7 @@
  * Marius Groeger <mgroeger@sysgo.de>
  *
  * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -32,62 +32,13 @@
 #include <common.h>
 #include <command.h>
 #include <arm926ejs.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-       unsigned long value;
-
-       __asm__ __volatile__(
-               "mrc    p15, 0, %0, c1, c0, 0   @ read control reg\n"
-               : "=r" (value)
-               :
-               : "memory");
-
-#ifdef MMU_DEBUG
-       printf ("p15/c1 is = %08lx\n", value);
-#endif
-       return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-#ifdef MMU_DEBUG
-       printf ("write %08lx to p15/c1\n", value);
-#endif
-       __asm__ __volatile__(
-               "mcr    p15, 0, %0, c1, c0, 0   @ write it back\n"
-               :
-               : "r" (value)
-               : "memory");
-
-       read_p15_c1 ();
-}
-
-static void cp_delay (void)
-{
-       volatile int i;
-
-       /* copro seems to need some delay between reading and writing */
-       for (i = 0; i < 100; i++);
-}
-
-/* See also ARM926EJ-S Technical Reference Manual */
-#define C1_MMU         (1<<0)          /* mmu off/on */
-#define C1_ALIGN       (1<<1)          /* alignment faults off/on */
-#define C1_DC          (1<<2)          /* dcache off/on */
-
-#define C1_BIG_ENDIAN  (1<<7)          /* big endian off/on */
-#define C1_SYS_PROT    (1<<8)          /* system protection */
-#define C1_ROM_PROT    (1<<9)          /* ROM protection */
-#define C1_IC          (1<<12)         /* icache off/on */
-#define C1_HIGH_VECTORS        (1<<13)         /* location of vectors: low/high addresses */
-
+static void cache_flush(void);
 
 int cpu_init (void)
 {
@@ -110,76 +61,22 @@ int cleanup_before_linux (void)
         * we turn off caches etc ...
         */
 
-       unsigned long i;
-
        disable_interrupts ();
 
-       /* turn off I/D-cache */
-       asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-       i &= ~(C1_DC | C1_IC);
-       asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
+       /* turn off I/D-cache */
+       icache_disable();
+       dcache_disable();
        /* flush I/D-cache */
-       i = 0;
-       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-
-       return (0);
-}
+       cache_flush();
 
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-       disable_interrupts ();
-       reset_cpu (0);
-       /*NOTREACHED*/
-       return (0);
-}
-
-/* cache_bit must be either C1_IC or C1_DC */
-static void cache_enable(uint32_t cache_bit)
-{
-       uint32_t reg;
-
-       reg = read_p15_c1();    /* get control reg. */
-       cp_delay();
-       write_p15_c1(reg | cache_bit);
-}
-
-/* cache_bit must be either C1_IC or C1_DC */
-static void cache_disable(uint32_t cache_bit)
-{
-       uint32_t reg;
-
-       reg = read_p15_c1();
-       cp_delay();
-       write_p15_c1(reg & ~cache_bit);
-}
-
-void icache_enable(void)
-{
-       cache_enable(C1_IC);
-}
-
-void icache_disable(void)
-{
-       cache_disable(C1_IC);
-}
-
-int icache_status(void)
-{
-       return (read_p15_c1() & C1_IC) != 0;
-}
-
-void dcache_enable(void)
-{
-       cache_enable(C1_DC);
+       return 0;
 }
 
-void dcache_disable(void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-       cache_disable(C1_DC);
-}
+       unsigned long i = 0;
 
-int dcache_status(void)
-{
-       return (read_p15_c1() & C1_DC) != 0;
+       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
 }