fec_mxc: cleanup and factor out imx27 dependencies

[u-boot] / cpu / arm926ejs / mx27 / generic.c

diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
index eab54d86df4bed2726ea44e4bb0b4dc3461bdcaf..30cf54471212adea3865fcd7e6d61d8557873ba9 100644 (file)
--- a/cpu/arm926ejs/mx27/generic.c
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -20,8 +20,12 @@
 
 #include <common.h>
 #include <div64.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#ifdef CONFIG_MXC_MMC
+#include <asm/arch/mxcmmc.h>
+#endif
 
 /*
  *  get the system pll clock in Hz
@@ -159,6 +163,33 @@ int print_cpuinfo (void)
 }
 #endif
 
+int cpu_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FEC_MXC)
+       struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+       /* enable FEC clock */
+       writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
+       writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
+       return fecmxc_initialize(bis);
+#else
+       return 0;
+#endif
+}
+
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_MXC_MMC
+       return mxc_mmc_init(bis);
+#else
+       return 0;
+#endif
+}
+
 void imx_gpio_mode(int gpio_mode)
 {
        struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
@@ -239,3 +270,66 @@ void imx_gpio_mode(int gpio_mode)
        }
 }
 
+#ifdef CONFIG_MXC_UART
+void mx27_uart_init_pins(void)
+{
+       int i;
+       unsigned int mode[] = {
+               PE12_PF_UART1_TXD,
+               PE13_PF_UART1_RXD,
+       };
+
+       for (i = 0; i < ARRAY_SIZE(mode); i++)
+               imx_gpio_mode(mode[i]);
+
+}
+#endif /* CONFIG_MXC_UART */
+
+#ifdef CONFIG_FEC_MXC
+void mx27_fec_init_pins(void)
+{
+       int i;
+       unsigned int mode[] = {
+               PD0_AIN_FEC_TXD0,
+               PD1_AIN_FEC_TXD1,
+               PD2_AIN_FEC_TXD2,
+               PD3_AIN_FEC_TXD3,
+               PD4_AOUT_FEC_RX_ER,
+               PD5_AOUT_FEC_RXD1,
+               PD6_AOUT_FEC_RXD2,
+               PD7_AOUT_FEC_RXD3,
+               PD8_AF_FEC_MDIO,
+               PD9_AIN_FEC_MDC | GPIO_PUEN,
+               PD10_AOUT_FEC_CRS,
+               PD11_AOUT_FEC_TX_CLK,
+               PD12_AOUT_FEC_RXD0,
+               PD13_AOUT_FEC_RX_DV,
+               PD14_AOUT_FEC_CLR,
+               PD15_AOUT_FEC_COL,
+               PD16_AIN_FEC_TX_ER,
+               PF23_AIN_FEC_TX_EN,
+       };
+
+       for (i = 0; i < ARRAY_SIZE(mode); i++)
+               imx_gpio_mode(mode[i]);
+}
+#endif /* CONFIG_FEC_MXC */
+
+#ifdef CONFIG_MXC_MMC
+void mx27_sd2_init_pins(void)
+{
+       int i;
+       unsigned int mode[] = {
+               PB4_PF_SD2_D0,
+               PB5_PF_SD2_D1,
+               PB6_PF_SD2_D2,
+               PB7_PF_SD2_D3,
+               PB8_PF_SD2_CMD,
+               PB9_PF_SD2_CLK,
+       };
+
+       for (i = 0; i < ARRAY_SIZE(mode); i++)
+               imx_gpio_mode(mode[i]);
+
+}
+#endif /* CONFIG_MXC_MMC */