move L2 cache enable/disable function to cache.c in the omap3 SoC directory

[u-boot] / cpu / arm_cortexa8 / cpu.c

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 6fd07d0b7375fa01d4d192769777f63c89fd99c9..fcb5775a1c3be37a2d00ddc0b004beaee7813bb2 100644 (file)
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -33,12 +33,8 @@
 
 #include <common.h>
 #include <command.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/system.h>
-
-#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
-#endif
+#include <asm/cache.h>
 
 static void cache_flush(void);
 
@@ -63,7 +59,7 @@ int cleanup_before_linux(void)
 
 #ifndef CONFIG_L2_OFF
        /* turn off L2 cache */
-       l2cache_disable();
+       l2_cache_disable();
        /* invalidate L2 cache also */
        v7_flush_dcache_all(get_device_type());
 #endif
@@ -72,72 +68,14 @@ int cleanup_before_linux(void)
        asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
 
 #ifndef CONFIG_L2_OFF
-       l2cache_enable();
+       l2_cache_enable();
 #endif
 
        return 0;
 }
 
-void l2cache_enable()
-{
-       unsigned long i;
-       volatile unsigned int j;
-
-       /* ES2 onwards we can disable/enable L2 ourselves */
-       if (get_cpu_rev() >= CPU_3XX_ES20) {
-               __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-               __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
-               __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-       } else {
-               /* Save r0, r12 and restore them after usage */
-               __asm__ __volatile__("mov %0, r12":"=r"(j));
-               __asm__ __volatile__("mov %0, r0":"=r"(i));
-
-               /*
-                * GP Device ROM code API usage here
-                * r12 = AUXCR Write function and r0 value
-                */
-               __asm__ __volatile__("mov r12, #0x3");
-               __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-               __asm__ __volatile__("orr r0, r0, #0x2");
-               /* SMI instruction to call ROM Code API */
-               __asm__ __volatile__(".word 0xE1600070");
-               __asm__ __volatile__("mov r0, %0":"=r"(i));
-               __asm__ __volatile__("mov r12, %0":"=r"(j));
-       }
-
-}
-
-void l2cache_disable()
-{
-       unsigned long i;
-       volatile unsigned int j;
-
-       /* ES2 onwards we can disable/enable L2 ourselves */
-       if (get_cpu_rev() >= CPU_3XX_ES20) {
-               __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-               __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
-               __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-       } else {
-               /* Save r0, r12 and restore them after usage */
-               __asm__ __volatile__("mov %0, r12":"=r"(j));
-               __asm__ __volatile__("mov %0, r0":"=r"(i));
-
-               /*
-                * GP Device ROM code API usage here
-                * r12 = AUXCR Write function and r0 value
-                */
-               __asm__ __volatile__("mov r12, #0x3");
-               __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-               __asm__ __volatile__("bic r0, r0, #0x2");
-               /* SMI instruction to call ROM Code API */
-               __asm__ __volatile__(".word 0xE1600070");
-               __asm__ __volatile__("mov r0, %0":"=r"(i));
-               __asm__ __volatile__("mov r12, %0":"=r"(j));
-       }
-}
-
 static void cache_flush(void)
 {
        asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
+