#include <i2c.h>
extern omap3_sysinfo sysinfo;
-static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
-static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
static char *rev_s[CPU_3XX_MAX_REV] = {
"1.0",
"2.0",
*****************************************************************/
void dieid_num_r(void)
{
- ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE;
+ struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
char *uid_s, die_id[34];
u32 id[4];
u32 get_cpu_rev(void)
{
u32 cpuid = 0;
- ctrl_id_t *id_base;
+ struct ctrl_id *id_base;
/*
* On ES1.0 the IDCODE register is not exposed on L4
return CPU_3XX_ES10;
else {
/* Decode the IDs on > ES1.0 */
- id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
+ id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
****************************************************/
u32 is_mem_sdr(void)
{
- if (readl(&sdrc_base->cs[CS0].mr) == SDP_SDRC_MR_0_SDR)
+ if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
return 1;
return 0;
}
/* get ram size field */
size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
size &= 0x3FF; /* remove unwanted bits */
- size *= SZ_2M; /* find size in MB */
+ size <<= 21; /* multiply by 2 MiB to find size in MB */
return size;
}
{
u32 b;
- b = readl(&gpmc_base->cs[0].config7);
+ b = readl(&gpmc_cfg->cs[0].config7);
b &= 0x1F; /* keep base [5:0] */
b = b << 24; /* ret 0x0b000000 */
return b;