* Cleanup lowboot code for MPC5200

[u-boot] / cpu / coldfire / start.S

diff --git a/cpu/coldfire/start.S b/cpu/coldfire/start.S
index 7e02661e0a3f6964183303ad8f26d4de6853928b..44542231db9237dfb81660531f4c4890c7ec1723 100644 (file)
--- a/cpu/coldfire/start.S
+++ b/cpu/coldfire/start.S
@@ -14,7 +14,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -26,8 +26,8 @@
 #include <config.h>
 #include "version.h"
 
-#ifndef  CONFIG_IDENT_STRING
-#define  CONFIG_IDENT_STRING ""
+#ifndef         CONFIG_IDENT_STRING
+#define         CONFIG_IDENT_STRING ""
 #endif
 
 #define MCF_MBAR 0x10000000
@@ -38,30 +38,30 @@
 
        .text
 
-        .globl  _start
+       .globl  _start
 _start:
        nop
        nop
        move.w #0x2700,%sr
 
-        move.l  #0, %d0
-        movec   %d0, %VBR
+       move.l  #0, %d0
+       movec   %d0, %VBR
 
 #ifdef CONFIG_M5272
-       move.l  #(MCF_MBAR+1), %d0
-        move.c  %d0, %MBAR
-
-       move.l  #(MEM_BUILTIN_ADDR+1), %d0
-        movec   %d0, %RAMBAR0
-
-       move.l  #0x01000000, %d0                /* Invalidate cache cmd */
-        movec   %d0, %CACR                      /* Invalidate cache */
-        move.l  #0x0000c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR0                      /* Enable cache */
-        move.l  #0xff00c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR1                      /* Enable cache */
-        move.l  #0x80000100, %d0                /* Setup cache mask */
-        movec   %d0, %CACR                      /* Enable cache */
+       move.l  #(MCF_MBAR+1), %d0
+       move.c  %d0, %MBAR
+
+       move.l  #(MEM_BUILTIN_ADDR+1), %d0
+       movec   %d0, %RAMBAR0
+
+       move.l  #0x01000000, %d0                /* Invalidate cache cmd */
+       movec   %d0, %CACR                      /* Invalidate cache */
+       move.l  #0x0000c000, %d0                /* Setup cache mask */
+       movec   %d0, %ACR0                      /* Enable cache */
+       move.l  #0xff00c000, %d0                /* Setup cache mask */
+       movec   %d0, %ACR1                      /* Enable cache */
+       move.l  #0x80000100, %d0                /* Setup cache mask */
+       movec   %d0, %CACR                      /* Enable cache */
 #endif
 
        move.l  #_sbss,%a0
@@ -71,8 +71,8 @@ _start:
        cmp.l   %a0,%d0
        bne.s   1b
 
-/*     move.l  #MEM_BUILTIN_ADDR+MEM_BUILTIN_SIZE, %sp */
-       move.l  #DRAM_ADDR+DRAM_SIZE, %sp
+/*     move.l  #MEM_BUILTIN_ADDR+MEM_BUILTIN_SIZE, %sp */
+       move.l  #DRAM_ADDR+DRAM_SIZE, %sp
        clr.l %sp@-
 
        jsr board_init_f
@@ -107,44 +107,44 @@ addresserror_handler:
        lea %sp@(60),%sp
        rte
 
-       .globl  get_endaddr
+       .globl  get_endaddr
 get_endaddr:
        movel #_end,%d0
        rts
 
 #ifdef CONFIG_M5272
-       .globl  icache_enable
+       .globl  icache_enable
 icache_enable:
-       move.l  #0x01000000, %d0                /* Invalidate cache cmd */
-        movec   %d0, %CACR                      /* Invalidate cache */
-        move.l  #0x0000c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR0                      /* Enable cache */
-        move.l  #0xff00c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR1                      /* Enable cache */
-        move.l  #0x80000100, %d0                /* Setup cache mask */
-        movec   %d0, %CACR                      /* Enable cache */
+       move.l  #0x01000000, %d0                /* Invalidate cache cmd */
+       movec   %d0, %CACR                      /* Invalidate cache */
+       move.l  #0x0000c000, %d0                /* Setup cache mask */
+       movec   %d0, %ACR0                      /* Enable cache */
+       move.l  #0xff00c000, %d0                /* Setup cache mask */
+       movec   %d0, %ACR1                      /* Enable cache */
+       move.l  #0x80000100, %d0                /* Setup cache mask */
+       movec   %d0, %CACR                      /* Enable cache */
        moveq   #1, %d0
        move.l  %d0, icache_state
        rts
 
-       .globl  icache_disable
+       .globl  icache_disable
 icache_disable:
-        move.l  #0x00000100, %d0                /* Setup cache mask */
-        movec   %d0, %CACR                      /* Enable cache */
-       clr.l   %d0                             /* Setup cache mask */
-        movec   %d0, %ACR0                      /* Enable cache */
-        movec   %d0, %ACR1                      /* Enable cache */
+       move.l  #0x00000100, %d0                /* Setup cache mask */
+       movec   %d0, %CACR                      /* Enable cache */
+       clr.l   %d0                             /* Setup cache mask */
+       movec   %d0, %ACR0                      /* Enable cache */
+       movec   %d0, %ACR1                      /* Enable cache */
        moveq   #0, %d0
        move.l  %d0, icache_state
        rts
 #endif
 
 #ifdef CONFIG_M5282
-       .globl  icache_enable
+       .globl  icache_enable
 icache_enable:
        rts
 
-       .globl  icache_disable
+       .globl  icache_disable
 icache_disable:
        rts
 #endif
@@ -158,7 +158,7 @@ icache_status:
 icache_state:
        .long   1
 
-       .globl  version_string
+       .globl  version_string
 version_string:
        .ascii U_BOOT_VERSION
        .ascii " (", __DATE__, " - ", __TIME__, ")"