#include <version.h>
#include <asm/arch/ixp425.h>
-#define MMU_Control_M 0x001 // Enable MMU
-#define MMU_Control_A 0x002 // Enable address alignment faults
-#define MMU_Control_C 0x004 // Enable cache
-#define MMU_Control_W 0x008 // Enable write-buffer
-#define MMU_Control_P 0x010 // Compatability: 32 bit code
-#define MMU_Control_D 0x020 // Compatability: 32 bit data
-#define MMU_Control_L 0x040 // Compatability:
-#define MMU_Control_B 0x080 // Enable Big-Endian
-#define MMU_Control_S 0x100 // Enable system protection
-#define MMU_Control_R 0x200 // Enable ROM protection
-#define MMU_Control_I 0x1000 // Enable Instruction cache
-#define MMU_Control_X 0x2000 // Set interrupt vectors at 0xFFFF0000
+#define MMU_Control_M 0x001 /* Enable MMU */
+#define MMU_Control_A 0x002 /* Enable address alignment faults */
+#define MMU_Control_C 0x004 /* Enable cache */
+#define MMU_Control_W 0x008 /* Enable write-buffer */
+#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
+#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
+#define MMU_Control_L 0x040 /* Compatability: */
+#define MMU_Control_B 0x080 /* Enable Big-Endian */
+#define MMU_Control_S 0x100 /* Enable system protection */
+#define MMU_Control_R 0x200 /* Enable ROM protection */
+#define MMU_Control_I 0x1000 /* Enable Instruction cache */
+#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
/*
* Macro definitions
*/
- // Delay a bit
- .macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
- .endm
-
- // wait for coprocessor write complete
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
+ /* Delay a bit */
+ .macro DELAY_FOR cycles, reg0
+ ldr \reg0, =\cycles
+ subs \reg0, \reg0, #1
+ subne pc, pc, #0xc
+ .endm
+
+ /* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
.globl _start
_start: b reset
.word _start
/*
- * Note: _armboot_end_data and _armboot_end are defined
- * by the (board-dependent) linker script.
- * _armboot_end_data is the first usable FLASH address after armboot
- */
-.globl _armboot_end_data
-_armboot_end_data:
- .word armboot_end_data
-.globl _armboot_end
-_armboot_end:
- .word armboot_end
-
-/*
- * This is defined in the board specific linker script
+ * These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
- .word bss_start
+ .word __bss_start
.globl _bss_end
_bss_end:
- .word bss_end
-
-/*
- * _armboot_real_end is the first usable RAM address behind armboot
- * and the various stacks
- */
-.globl _armboot_real_end
-_armboot_real_end:
- .word 0x0badc0de
-
-/*
- * We relocate uboot to this address (end of RAM - 128 KiB)
- */
-.globl _uboot_reloc
-_uboot_reloc:
- .word TEXT_BASE
+ .word _end
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
/* disable mmu, set big-endian */
mov r0, #0xf8
mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
+ CPWAIT r0
/* invalidate I & D caches & BTB */
mcr p15, 0, r0, c7, c7, 0
CPWAIT r0
/* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
+ mcr p15, 0, r0, c8, c7, 0
+ CPWAIT r0
/* drain write and fill buffers */
mcr p15, 0, r0, c7, c10, 4
CPWAIT r0
/* set EXP CS0 to the optimum timing */
- ldr r1, =CFG_EXP_CS0
+ ldr r1, =CONFIG_SYS_EXP_CS0
ldr r2, =IXP425_EXP_CS0
str r1, [r2]
- /* make sure flash is visible at 0 */
- ldr r2, =IXP425_EXP_CFG0
+ /* make sure flash is visible at 0 */
+#if 0
+ ldr r2, =IXP425_EXP_CFG0
ldr r1, [r2]
orr r1, r1, #0x80000000
str r1, [r2]
-
- mov r1, #CFG_SDR_CONFIG
+#endif
+ mov r1, #CONFIG_SYS_SDR_CONFIG
ldr r2, =IXP425_SDR_CONFIG
str r1, [r2]
/* disable refresh cycles */
- mov r1, #0
+ mov r1, #0
ldr r3, =IXP425_SDR_REFRESH
str r1, [r3]
/* send nop command */
- mov r1, #3
+ mov r1, #3
ldr r4, =IXP425_SDR_IR
str r1, [r4]
- DELAY_FOR 0x4000, r0
+ DELAY_FOR 0x4000, r0
/* set SDRAM internal refresh val */
- ldr r1, =CFG_SDRAM_REFRESH_CNT
+ ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
str r1, [r3]
DELAY_FOR 0x4000, r0
bne 111b
/* set mode register in sdram */
- mov r1, #1
+ mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
str r1, [r4]
DELAY_FOR 0x4000, r0
DELAY_FOR 0x4000, r0
/* copy */
- mov r0, #0
- mov r4, r0
- add r2, r0, #0x40000
+ mov r0, #0
+ mov r4, r0
+ add r2, r0, #CONFIG_SYS_MONITOR_LEN
mov r1, #0x10000000
- mov r5, r1
+ mov r5, r1
30:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r0, r2
- bne 30b
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r0, r2
+ bne 30b
/* invalidate I & D caches & BTB */
mcr p15, 0, r0, c7, c7, 0
CPWAIT r0
/* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
+ mcr p15, 0, r0, c8, c7, 0
+ CPWAIT r0
/* drain write and fill buffers */
mcr p15, 0, r0, c7, c10, 4
CPWAIT r0
- /* move flash to 0x50000000 */
- ldr r2, =IXP425_EXP_CFG0
+ /* move flash to 0x50000000 */
+ ldr r2, =IXP425_EXP_CFG0
ldr r1, [r2]
bic r1, r1, #0x80000000
str r1, [r2]
nop
/* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
+ mcr p15, 0, r0, c8, c7, 0
+ CPWAIT r0
- /* enable I cache */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #MMU_Control_I
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
+ /* enable I cache */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #MMU_Control_I
+ mcr p15, 0, r0, c1, c0, 0
+ CPWAIT r0
mrs r0,cpsr /* set the cpu to SVC32 mode */
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
orr r0,r0,#0x13
msr cpsr,r0
+#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
beq stack_setup
ldr r2, _armboot_start
- ldr r3, _armboot_end
+ ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end addreee [r2] */
ble copy_loop
+#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
-
stack_setup:
-
- ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
- /* FIXME: bdinfo should be here */
+ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
+#ifdef CONFIG_USE_IRQ
+ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
+#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
-
ldr r0, _bss_start /* find start of bss segment */
- add r0, r0, #4 /* start at first byte of bss */
ldr r1, _bss_end /* stop here */
- mov r2, #0x00000000 /* clear */
+ mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- bne clbss_l
-
+ ble clbss_l
ldr pc, _start_armboot
_start_armboot: .word start_armboot
-
-
/****************************************************************************/
/* */
/* Interrupt handling */
stmia sp, {r0 - r12} /* Calling r0-r12 */
add r8, sp, #S_PC
- ldr r2, _armboot_end
- add r2, r2, #CONFIG_STACKSIZE
- sub r2, r2, #8
+ ldr r2, _armboot_start
+ sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
.endm
.macro get_bad_stack
- ldr r13, _armboot_end @ setup our mode stack
- add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
- sub r13, r13, #8
+ ldr r13, _armboot_start @ setup our mode stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
.globl reset_cpu
reset_cpu:
- ldr r1, =0x482e
+ ldr r1, =0x482e
ldr r2, =IXP425_OSWK
str r1, [r2]
- ldr r1, =0x0fff
+ ldr r1, =0x0fff
ldr r2, =IXP425_OSWT
str r1, [r2]
- ldr r1, =0x5
+ ldr r1, =0x5
ldr r2, =IXP425_OSWE
str r1, [r2]
b reset_endless
reset_endless:
b reset_endless
+
+#ifdef CONFIG_USE_IRQ
+
+.LC0: .word loops_per_jiffy
+
+/*
+ * 0 <= r0 <= 2000
+ */
+.globl __udelay
+__udelay:
+ mov r2, #0x6800
+ orr r2, r2, #0x00db
+ mul r0, r2, r0
+ ldr r2, .LC0
+ ldr r2, [r2] @ max = 0x0fffffff
+ mov r0, r0, lsr #11 @ max = 0x00003fff
+ mov r2, r2, lsr #11 @ max = 0x0003ffff
+ mul r0, r2, r0 @ max = 2^32-1
+ movs r0, r0, lsr #6
+
+delay_loop:
+ subs r0, r0, #1
+ bne delay_loop
+ mov pc, lr
+
+#endif /* CONFIG_USE_IRQ */
projects / u-boot / blobdiff