cpu/ non-mpc*: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*).

[u-boot] / cpu / mcf52x2 / fec.c

diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c
index f207dd6acb59e0b825a5c7e07ecf755a25b36f2b..36270712e0ae1660e0a77a704b104ddad2e53591 100644 (file)
--- a/cpu/mcf52x2/fec.c
+++ b/cpu/mcf52x2/fec.c
@@ -53,7 +53,7 @@
 #undef ET_DEBUG
 #undef MII_DEBUG
 
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
+#if ((CONFIG_COMMANDS & CFG_CMD_NET)  || defined(CONFIG_CMD_NET)) && defined(FEC_ENET)
 
 #ifdef CFG_DISCOVER_PHY
 #include <miiphy.h>
@@ -205,7 +205,9 @@ int eth_rx (void)
 
 int eth_init (bd_t * bd)
 {
-
+#ifndef CFG_ENET_BD_BASE
+       DECLARE_GLOBAL_DATA_PTR;
+#endif
        int i;
        volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
 
@@ -258,8 +260,13 @@ int eth_init (bd_t * bd)
 #else
        /* Clear multicast address hash table
         */
+#ifdef CONFIG_M5282
+       fecp->fec_ihash_table_high = 0;
+       fecp->fec_ihash_table_low = 0;
+#else
        fecp->fec_hash_table_high = 0;
        fecp->fec_hash_table_low = 0;
+#endif
 #endif
 
        /* Set maximum receive buffer size.
@@ -273,7 +280,16 @@ int eth_init (bd_t * bd)
        txIdx = 0;
 
        if (!rtx) {
+#ifdef CFG_ENET_BD_BASE
                rtx = (RTXBD *) CFG_ENET_BD_BASE;
+#else
+               rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off -
+                                (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t)
+                                 +0xFF)
+                                 & ~0xFF)
+                               );
+               debug("set ENET_DB_BASE to %lX\n",(long) rtx);
+#endif
        }
 
        /*
@@ -307,18 +323,18 @@ int eth_init (bd_t * bd)
 
        /* Enable MII mode
         */
-#if 0                          /* Full duplex mode */
+
+#if 0  /* Full duplex mode */
        fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
        fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
-#else  /* Half duplex mode */
-       fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
-#ifdef CONFIG_M5271
-       fecp->fec_r_cntrl |= (PKT_MAXBUF_SIZE << 16); /* set max frame length */
-#endif
+#else  /* Half duplex mode */
+       fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */
+       fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
        fecp->fec_x_cntrl = 0;
 #endif
        /* Set MII speed */
-       fecp->fec_mii_speed = 0x0e;
+       fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10;
+       fecp->fec_mii_speed *= 2;
 
        /* Configure port B for MII.
         */
@@ -347,7 +363,7 @@ void eth_halt (void)
 }
 
 
-#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)
 
 static int phyaddr = -1;       /* didn't find a PHY yet */
 static uint phytype;
@@ -422,7 +438,7 @@ static void mii_discover_phy (void)
                         */
                        udelay (10000); /* wait 10ms */
                }
-               for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
+               for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) {
                        phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
 #ifdef ET_DEBUG
                        printf ("PHY type 0x%x pass %d type ", phytype, pass);
@@ -469,7 +485,7 @@ static void mii_discover_phy (void)
 }
 #endif /* CFG_DISCOVER_PHY */
 
-#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
+#if ((CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
 
 static int mii_init_done = 0;
 
@@ -580,8 +596,8 @@ int mcf52x2_miiphy_write (char *devname, unsigned char addr,
 
 int mcf52x2_miiphy_initialize(bd_t *bis)
 {
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
-#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
+#if ((CONFIG_COMMANDS & CFG_CMD_NET) || defined(CONFIG_CMD_NET)) && defined(FEC_ENET)
+#if ((CONFIG_COMMANDS & CFG_CMD_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII)
        miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
 #endif
 #endif