ColdFire: Add M5208EVB and MCF520x CPU support

[u-boot] / cpu / mcf52x2 / start.S

diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index ba6b8843e42e37bb8b810e6a4ad0bc6d0201cbee..0dd4de5160c0d209de8564cd301100bb8a24d488 100644 (file)
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -120,6 +120,12 @@ _start:
        nop
        move.w #0x2700,%sr
 
+#if defined(CONFIG_M5208)
+       /* Initialize RAMBAR: locate SRAM and validate it */
+       move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+       movec   %d0, %RAMBAR1
+#endif
+
 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
        move.l  #(CONFIG_SYS_MBAR + 1), %d0             /* set MBAR address + valid flag */
        move.c  %d0, %MBAR
@@ -195,15 +201,6 @@ _after_flashbar_copy:
        movec   %d0, %RAMBAR1
 #endif
 
-#if 0
-       /* invalidate and disable cache */
-       move.l  #0x01000000, %d0                /* Invalidate cache cmd */
-       movec   %d0, %CACR                      /* Invalidate cache */
-       move.l  #0, %d0
-       movec   %d0, %ACR0
-       movec   %d0, %ACR1
-#endif
-
        /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
        move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
        clr.l %sp@-
@@ -340,6 +337,24 @@ _int_handler:
 
 /*------------------------------------------------------------------------------*/
 /* cache functions */
+#ifdef CONFIG_M5208
+       .globl  icache_enable
+icache_enable:
+       move.l  #0x01000000, %d0                /* Invalidate cache cmd */
+       movec   %d0, %CACR                      /* Invalidate cache */
+       move.l  #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0  /* Setup cache mask */
+       movec   %d0, %ACR0                      /* Enable cache */
+
+       move.l  #0x80000200, %d0                /* Setup cache mask */
+       movec   %d0, %CACR                      /* Enable cache */
+       nop
+
+       move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
+       moveq   #1, %d0
+       move.l  %d0, (%a1)
+       rts
+#endif
+
 #ifdef CONFIG_M5271
        .globl  icache_enable
 icache_enable: