ppc/85xx: add cpu init config file for boot from NAND

[u-boot] / cpu / mcf5445x / cpu_init.c

diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 50b4561f3fd43d1a32cfe3cc547c8df73636598d..48b37dfe7dd951ed7c65000dd344e97be54b62a3 100644 (file)
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -27,10 +27,15 @@
 
 #include <common.h>
 #include <watchdog.h>
-
 #include <asm/immap.h>
 #include <asm/rtc.h>
 
+#if defined(CONFIG_CMD_NET)
+#include <config.h>
+#include <net.h>
+#include <asm/fec.h>
+#endif
+
 /*
  * Breath some life into the CPU...
  *
@@ -139,3 +144,96 @@ void uart_port_conf(void)
                break;
        }
 }
+
+#if defined(CONFIG_CMD_NET)
+int fecpin_setclear(struct eth_device *dev, int setclear)
+{
+       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+
+       if (setclear) {
+               gpio->par_feci2c |=
+                   (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+
+               if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+                       gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
+               else
+                       gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
+       } else {
+               gpio->par_feci2c &=
+                   ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+
+               if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
+                       gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
+               else
+                       gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
+       }
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_CF_DSPI
+void cfspi_port_conf(void)
+{
+       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+       gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+           GPIO_PAR_DSPI_SCK_SCK;
+}
+
+int cfspi_claim_bus(uint bus, uint cs)
+{
+       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+       if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+               return -1;
+
+       /* Clear FIFO and resume transfer */
+       dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+
+       switch (cs) {
+       case 0:
+               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+               gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+               break;
+       case 1:
+               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+               gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
+               break;
+       case 2:
+               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+               gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
+               break;
+       case 5:
+               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+               gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
+               break;
+       }
+
+       return 0;
+}
+
+void cfspi_release_bus(uint bus, uint cs)
+{
+       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+       dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);  /* Clear FIFO */
+
+       switch (cs) {
+       case 0:
+               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+               break;
+       case 1:
+               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
+               break;
+       case 2:
+               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
+               break;
+       case 5:
+               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
+               break;
+       }
+}
+#endif