[MIPS] Request for the 'mips_cache_lock()' removal

[u-boot] / cpu / mips / cache.S

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 55daa89e7290d555622f163e3c1b77ee53aba663..67ee19fba8ea819d2ee162697e8232fb0d96e87a 100644 (file)
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -22,7 +22,6 @@
  * MA 02111-1307 USA
  */
 
-
 #include <config.h>
 #include <version.h>
 #include <asm/regdef.h>
@@ -30,13 +29,11 @@
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
 
-
        /* 16KB is the maximum size of instruction and data caches on
         * MIPS 4K.
         */
 #define MIPS_MAX_CACHE_SIZE    0x4000
 
-
 /*
  * cacheop macro to automate cache operations
  * first some helpers...
@@ -131,7 +128,6 @@ mips_cache_reset:
        li      t4, CFG_CACHELINE_SIZE
        move    t5, t4
 
-
        li      v0, MIPS_MAX_CACHE_SIZE
 
        /* Now clear that much memory starting from zero.
@@ -139,8 +135,8 @@ mips_cache_reset:
 
        li      a0, KSEG1
        addu    a1, a0, v0
-
-2:     sw      zero, 0(a0)
+2:
+       sw      zero, 0(a0)
        sw      zero, 4(a0)
        sw      zero, 8(a0)
        sw      zero, 12(a0)
@@ -150,17 +146,17 @@ mips_cache_reset:
        sw      zero, 28(a0)
        addu    a0, 32
        bltu    a0, a1, 2b
-   
+
        /* Set invalid tag.
         */
 
        mtc0    zero, CP0_TAGLO
 
-   /*
-    * The caches are probably in an indeterminate state,
-    * so we force good parity into them by doing an
-    * invalidate, load/fill, invalidate for each line.
-    */
+       /*
+        * The caches are probably in an indeterminate state,
+        * so we force good parity into them by doing an
+        * invalidate, load/fill, invalidate for each line.
+        */
 
        /* Assume bottom of RAM will generate good parity for the cache.
         */
@@ -201,9 +197,9 @@ mips_cache_reset:
        move    a1, a2
        icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
 
-       j  ra
-       .end  mips_cache_reset
+       j       ra
 
+       .end    mips_cache_reset
 
 /*******************************************************************************
 *
@@ -220,7 +216,7 @@ dcache_status:
        andi    v0, v0, 1
        j       ra
 
-       .end  dcache_status
+       .end    dcache_status
 
 /*******************************************************************************
 *
@@ -237,12 +233,12 @@ dcache_disable:
        li      t1, -8
        and     t0, t0, t1
        ori     t0, t0, CONF_CM_UNCACHED
-       mtc0    t0, CP0_CONFIG
+       mtc0    t0, CP0_CONFIG
        j       ra
 
-       .end  dcache_disable
-
+       .end    dcache_disable
 
+#ifdef CFG_INIT_RAM_LOCK_MIPS
 /*******************************************************************************
 *
 * mips_cache_lock - lock RAM area pointed to by a0 in cache.
@@ -250,10 +246,10 @@ dcache_disable:
 * RETURNS: N/A
 *
 */
-#if defined(CONFIG_INCA_IP)
-# define       CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
-#elif defined(CONFIG_PURPLE)
+#if defined(CONFIG_PURPLE)
 # define       CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
+#else
+# define       CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
 #endif
        .globl  mips_cache_lock
        .ent    mips_cache_lock
@@ -266,5 +262,6 @@ mips_cache_lock:
        icacheop(a0,a1,a2,a3,0x1d)
 
        j       ra
-       .end    mips_cache_lock
 
+       .end    mips_cache_lock
+#endif /* CFG_INIT_RAM_LOCK_MIPS */